Power bus maximum voltage drop in digital VLSI circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 263-268

  Bai, G ^a   Bobba, S ^a   Hajj, I N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SENSITIVITY ANALYSIS; SPICE; TIMING CIRCUITS; VOLTAGE MEASUREMENT;

CIRCUIT DELAYS; CIRCUIT FUNCTIONALITY; CIRCUIT TIMING; CLOCK CYCLES; EXHAUSTIVE SIMULATION; GATE CURRENT; PRIMARY INPUTS; STATISTICAL VARIATIONS;

VLSI CIRCUITS;

EID: 0002885199     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2000.838881     Document Type: Article

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