A Statistical Critical Dimension Control at CMOS Cell Level

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 631-634

  Misaka, A ^a   Goda, A ^a   Matsuoka, K ^a   Umimoto, H ^a   Odanaka, S ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SENSITIVITY ANALYSIS; GATES (TRANSISTOR); LITHOGRAPHY; SPATIAL VARIABLES CONTROL; STATISTICAL METHODS;

CELL LEVELS; CRITICAL DIMENSION CONTROL; GATE PATTERNS; LITHOGRAPHY PROCESS; RESPONSE SURFACE FUNCTIONS; STATISTICAL METHODOLOGIES;

LITHOGRAPHY; INTEGRATED CIRCUIT MANUFACTURE;

CRITICAL DIMENSION CONTROL; GATE PATTERNS; RESPONSE SURFACE FUNCTIONS;

EID: 0030416399     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554062     Document Type: Conference Paper

References (2)

1. M. Yeung: Proc. Kodak Microelectronics Seminar INTERFACE’S, 1986,p115
2. R. A.Cirelli: Proc. SPIE, Vol. 2197,1993,p429