Effect of code reordering on branch prediction

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2000, Pages 189-198

  Ramirez, Alex ^a   Larriba Pey, Josep L ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; HEURISTIC PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; RESPONSE TIME (COMPUTER SYSTEMS);

BRANCH HISTORY REGISTER; CODE REORDERING; DYNAMIC BRANCH PREDICTION; INSTRUCTION LEVEL PARALLELISM; PATTERN HISTORY TABLE; STATIC DYNAMIC PREDICTION;

INFORMATION RETRIEVAL SYSTEMS;

EID: 0034512996     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)