ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 32-43

  Ker, Ming Dou ^a   Chuang, Chien Hui ^a   Jiang, Hsin Chin ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Clamps; CMOS process; CMOS technology; Electrostatic discharge; Integrated circuit technology; MOS devices; Power supplies; Protection; Thyristors; Voltage

Indexed keywords

CLAMPING DEVICES; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT DESIGN; MOS DEVICES; THYRISTORS;

CMOS PROCESSS; CMOS TECHNOLOGY; INTEGRATED CIRCUIT TECHNOLOGY; POWER SUPPLY; PROTECTION;

ELECTRIC RECTIFIERS;

EID: 84948982796     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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