Versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1501-1511

  Sánchez, Héctor ^a   Siegel, Joshua ^a   Nicoletta, Carmine ^a   Nissen, James P ^a   Alvarez, José ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC GENERATORS; ELECTRIC SWITCHES; INTERFACES (COMPUTER); RESISTORS; SPURIOUS SIGNAL NOISE;

INPUT/OUTPUT DRIVERS; SWITCH CAPACITORS;

CMOS INTEGRATED CIRCUITS;

EID: 0343898028     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799854     Document Type: Article

References (4)

1. S. Venkatesan, A. V. Gelatos, V. Misra, B. Smith, R. Islam, J. Cope, B. Wilson, D. Tuttle, R. Cardwell, S. Anderson, M. Angyal, R. Bajaj, C. Capasso, P. Crabtree, S. Das, J. Farkas, S. Filipiak, B. Fiordalice, M. Freeman, P. V. Gilbert, M. Herrick, A. Jain, H. Kawasaki, C. King, J. Klein, T. Lii, K. Reid, T. Saaranen, C. Simpson, T. Sparks, P. Tsui, R. Venkatraman, D. Watts, E. J. Weitzman, R. Woodruff, I. Yang, N. Bhat, G. Hamilton, and Y. Yu, "A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization," in Proc. Int. Electron Devices Meeting, Dec. 7, 1997, pp. 770-772.
2. G. P. Singh and R. B. Salem, "A 1.9 V I/O buffer with gate-oxide protection and dynamic bus termination for 400 MHz ultraSPARC microprocessor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 16, 1999, pp. 274-275.
3. J. Alvarez, E. Barkin, C.-C. Chao, B. Johnson, M. D'Addeo, F. Lassandro, C. Nicoletta, P. Patel, P. Reed, D. Reid, H. Sanchez, J. Siegel, M. Snyder, S. Sullivan, S. Taylor, and M. Vo, "A 450 MHz PowerPC™ microprocessor with enhanced instruction set and copper interconnect," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 15, 1999, 88-89.
4. Y. Ohtomo, T. Mizusawa, K. Nishimura, H. Sawada, M. Ino, "A quartermicron SIMOX-CMOS LVTTL compatible gate array with an over 2,000 V ESD-protection circuit," in Proc. IEEE 1996 Custom Integrated Circuits Conf., pp. 57-60.