Accurate and efficient analysis of single event transients in VLSI circuits

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 101-105

  Sonza Reorda, M ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Analytical models; Circuit analysis; Circuit faults; Circuit simulation; Circuit topology; Fault diagnosis; Information analysis; Prototypes; Transient analysis; Very large scale integration

Indexed keywords

ANALYTICAL MODELS; CIRCUIT SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; FAILURE ANALYSIS; FAULT DETECTION; HIGH ELECTRON MOBILITY TRANSISTORS; INFORMATION ANALYSIS; RADIATION HARDENING; TOPOLOGY; TRANSIENT ANALYSIS; VLSI CIRCUITS;

CIRCUIT FAULTS; COMPLEX DESIGNS; DEEP SUB-MICRON TECHNOLOGY; EFFICIENT ANALYSIS; PROTOTYPES; SINGLE EVENT TRANSIENTS; TIME-RELATED INFORMATION; ZERO DELAY;

TRANSIENTS;

EID: 84944030713     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214374     Document Type: Conference Paper

References (11)

1. L. Anghel, M. Nicolaidis, "Cost Reduction of a Temporary Faults Detecting Technique", IEEE Design, Automation and Test in Europe Conference, 2000, pp. 591-598
2. Mei-Chen Hsueh, T.K Tsai, R.K Iyer, "Fault injection techniques and tools", IEEE Computer, Vol. 30, No. 4, 1997, pp. 75-82
3. P. Dahlgren, P. Liden, "A switch-level algorithm for simulation of transients in combination logic", IEEE Fault Tolerant Computing Symposium, 1995, pp. 207-216
4. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson, "Fault Injection into VHDL Models: the MEFISTO Tool", IEEE Fault Tolerant Computing Symposium, 1994, pp. 66-75
5. J. Boué, P. Pétillon, Y. Crouzet, "MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance", IEEE Fault-Tolerant Computing Symposium, 1998, pp. 168-173
6. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante, "Exploiting Circuit Emulation for Fast Hardness Evaluation", IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
7. L. Antoni, R. Leveugle, B. Fehér, "Using run-time reconfiguration for fault injection in hardware prototypes", IEEE Symp. on Defect and Fault Tolerance in VLSI Systems, 2000, pp. 405-413
8. L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, B. L. Bhuva, "Analysis of Single-Event Effects in Combinational Logic-Simulation of the AM2901 Bitslice Processor", IEEE Transactions on Nuclear Science, Vol. 47, No. 6, 2000, pp. 2609-2615
9. L. Berrojo, I. González, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez, "New Techniques for Speeding-up Fault-injection Campaigns", IEEE Design, Automation and Test in Europe, 2002, pp. 847-852
10. M. Sonza Reorda, M. Violante, "Fault list compaction through static timing analysis for efficient fault injection experiments", IEEE Symp. on Defect and Fault Tolerance in VLSI Systems, 2002, pp. 263-271
11. S. Manich, J. Figueras, "Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model", IEEE European Design and Test Conference, 1997, pp. 597-602