Fault list compaction through static timing analysis for efficient fault injection experiments

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 263-271

  Reorda, M S ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Circuit faults; Circuit simulation; Compaction; Error correction; Fault diagnosis; Formal verification; Prototypes; Timing; Transient analysis; Very large scale integration

Indexed keywords

CIRCUIT SIMULATION; COMPACTION; DEFECTS; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; FAILURE ANALYSIS; FAULT DETECTION; FAULT TOLERANCE; FORMAL VERIFICATION; HIGH ELECTRON MOBILITY TRANSISTORS; RADIATION HARDENING; SOFTWARE TESTING; TRANSIENT ANALYSIS; TRANSIENTS; VLSI CIRCUITS;

CIRCUIT FAULTS; DEEP SUB-MICRON TECHNOLOGY; FAULT INJECTION; NEW APPROACHES; PROTOTYPES; SINGLE EVENT TRANSIENTS; STATIC TIMING ANALYSIS; TIMING;

TIMING CIRCUITS;

EID: 84948959517     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173523     Document Type: Conference Paper

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