Switch-level algorithm for simulation of transients in combinational logic

Proceedings - Annual International Conference on Fault-Tolerant Computing

Volumn , Issue , 1995, Pages 207-216

  Dahlgren, Peter ^a   Liden, Peter ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; ERROR DETECTION; FAILURE ANALYSIS; LOGIC GATES; MATHEMATICAL MODELS; TRANSIENTS; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS;

DEVICE LEVEL TRANSIENTS EFFECTS; ELECTRICAL LEVEL TRANSIENT FAULT MODEL; FAULT PROPAGATION; FAULT SIMULATION; GATE LEVEL MODELING; SWITCH LEVEL ALGORITHM; ELECTRICAL LEVEL SIMULATION; FAULT DETECTION; FAULT INJECTION; GATE LEVEL SIMULATION; RC MODEL;

FAULT TOLERANT COMPUTER SYSTEMS; ALGORITHMS;

EID: 0028994255     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)