BIST-aided scan test - A new method for test cost reduction

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 359-364

  Hiraide, T ^a   Boateng, Kwame Osei ^a   Konishi, H ^a   Itaya, K ^a   Emori, M ^a   Yamanaka, H ^a   Mochiyama, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Automatic test pattern generation; Automatic testing; Built in self test; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Laboratories; Large scale integration; Logic testing

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; AUTOMATIC TESTING; COST REDUCTION; COSTS; INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; LABORATORIES; LSI CIRCUITS; VLSI CIRCUITS;

BIST TECHNIQUES; CIRCUIT FAULTS; CIRCUIT TESTING; DESIGN COMPLEXITY; FAULT COVERAGES; LOGIC TESTING; SCAN-BASED DESIGNS; TEST COST REDUCTION;

BUILT-IN SELF TEST;

EID: 84943579799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197675     Document Type: Conference Paper

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