Post-route gate sizing for crosstalk noise reduction

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 171-176

  Becer, Murat R ^a   Blaauw, David ^b   Algor, Ilan ^a   Panda, Rajendran ^a   Oh, Chanhee ^a   Zolotov, Vladimir ^a   Hajj, Ibrahim N ^c  

^a MOTOROLA INC   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Algorithm design and analysis; Capacitance; Circuit noise; Coupling circuits; Crosstalk; Delay; Driver circuits; Noise reduction; Routing; Wire

Indexed keywords

ALGORITHMS; CAPACITANCE; COUPLED CIRCUITS; CROSSTALK; DELAY CIRCUITS; DESIGN; ELECTRIC NETWORK ANALYSIS; GATES (TRANSISTOR); WIRE;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT NOISE; DELAY; DRIVER CIRCUIT; ROUTING;

NOISE ABATEMENT;

EID: 84942092488     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194727     Document Type: Conference Paper

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