-
2
-
-
0030410557
-
Interconnect capacitance, crosstalk, and signal delay for 0.35um CMOS technology
-
D. H. Cho, Y. S. Eo, N. H. Kim, J. K. Wee, O. K. Kwon, and H. S. Park, "Interconnect Capacitance, Crosstalk, and Signal Delay for 0.35um CMOS Technology", Proc. IEDM '96, pp.619-622.
-
Proc. IEDM '96
, pp. 619-622
-
-
Cho, D.H.1
Eo, Y.S.2
Kim, N.H.3
Wee, J.K.4
Kwon, O.K.5
Park, H.S.6
-
3
-
-
0006683552
-
Global interconnect sizing and spacing with consideration of coupling capacitance
-
J. Cong, L. Hei, C. K. Kok and Z.Pan, "Global Interconnect Sizing and spacing with Consideration of Coupling Capacitance", ICCAD 97, pp. 478-485.
-
ICCAD
, vol.97
, pp. 478-485
-
-
Cong, J.1
Hei, L.2
Kok, C.K.3
Pan, Z.4
-
4
-
-
34748823693
-
The transient response of damped linear networks with particular regard to wideband amplifiers
-
Jan-Dec
-
W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers", Journal of Applied Physics, Volume 19, Jan-Dec. 1948, p55-63.
-
(1948)
Journal of Applied Physics
, vol.19
, pp. 55-63
-
-
Elmore, W.C.1
-
5
-
-
85113891155
-
Tilos: A posynomial approach to transistor sizing
-
J. P. Fishburn, A. E. Dunlop, "TILOS: A Posynomial Approach to Transistor Sizing", Proceedings of ICCAD 85, p326-328.
-
Proceedings of ICCAD
, vol.85
, pp. 326-328
-
-
Fishburn, J.P.1
Dunlop, A.E.2
-
6
-
-
0028711539
-
Minimum crosstalk switchbox routing
-
T. Gao, C. Liu, "Minimum Crosstalk Switchbox Routing", Proc. ICCAD 94, page 610-615, 1994.
-
(1994)
Proc. ICCAD
, vol.94
, pp. 610-615
-
-
Gao, T.1
Liu, C.2
-
7
-
-
85037773866
-
-
NEOS guide, http://www-c.mcs.anl.gov/home/otc/Guide.
-
NEOS Guide
-
-
-
8
-
-
0003725604
-
-
Prentice-Hall, Inc
-
C. H. Papadimitriou, K. Steiglitz, "Combinatorial Optimization: Algorithms and Complexity", Prentice-Hall, Inc., 1982, pl7.
-
(1982)
Combinatorial Optimization: Algorithms and Complexity
, pp. l7
-
-
Papadimitriou, C.H.1
Steiglitz, K.2
-
9
-
-
0029510043
-
Coping with RC(L) interconnect design headaches
-
L. Pileggi, "Coping with RC(L) Interconnect Design Headaches", Proc. ICCAD 95, p246-253.
-
Proc. ICCAD
, vol.95
, pp. 246-253
-
-
Pileggi, L.1
-
10
-
-
0027222295
-
Closed-form expression for interconnection delay, coupling, and crosstalk in VLSI's
-
T. Sakurai, "Closed-Form Expression for Interconnection Delay, Coupling, and Crosstalk in VLSI's", IEEE Trans, on Electron Devices, vol. 40, no. 1, 1993, pp. 118-124.
-
(1993)
IEEE Trans, on Electron Devices
, vol.40
, Issue.1
, pp. 118-124
-
-
Sakurai, T.1
-
11
-
-
0003449348
-
-
Third edition, Harcourt Brace Jovanovich, Inc
-
G. Strang, "Linear Algebra and Its Applications", Third edition, Harcourt Brace Jovanovich, Inc., 1988, p339.
-
(1988)
Linear Algebra and Its Applications
, pp. 339
-
-
Strang, G.1
-
12
-
-
0027701389
-
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
-
S. S. Sapatnekar, "An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization", IEEE Trans, on CAD of IC and Systems, vol. 12, no. 11, 1993, pl621-1634.
-
(1993)
IEEE Trans, on CAD of IC and Systems
, vol.12
, Issue.11
, pp. l621-l1634
-
-
Sapatnekar, S.S.1
-
13
-
-
0023997018
-
Optimization-based transistor sizing
-
April
-
J. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn, "Optimization-Based Transistor Sizing", IEEE Journal of Solid-State Circuits, vol. 23, no. 2, April 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, Issue.2
-
-
Shyu, J.1
Sangiovanni-Vincentelli, A.2
Fishburn, J.P.3
-
14
-
-
0031099379
-
Crosstalk reduction for VLSI
-
March
-
A. Vittal, M. Marek-Sadowska, "Crosstalk Reduction for VLSI", IEEE Trans, on CAD, March, 1997, vol. 16, no. 3, pp. 290-298.
-
(1997)
IEEE Trans, on CAD
, vol.16
, Issue.3
, pp. 290-298
-
-
Vittal, A.1
Marek-Sadowska, M.2
-
15
-
-
85113878559
-
Crosstalk in resistive VLSI interconnections
-
to be
-
A Vittal, L.H.Chen,M. Marek-Sadowska, K.P.Wang and X. Yang, "Crosstalk in Resistive VLSI Interconnections", to be presented at 12th International Conference on VLSI Design.
-
12th International Conference on VLSI Design
-
-
Vittal, A.1
Chen, L.H.2
Marek-Sadowska, M.3
Wang, K.P.4
Yang, X.5
-
16
-
-
0030412696
-
Post global routing crosstalk risk estimation and reduction
-
T. Xue, E. S. Kuh and D. Wang, "Post Global Routing Crosstalk Risk Estimation and Reduction", Proc. ICCAD 96, pp. 302-309.
-
Proc. ICCAD
, vol.96
, pp. 302-309
-
-
Xue, T.1
Kuh, E.S.2
Wang, D.3
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