A circuit-based learning architecture for multilayer neural networks with memristor bridge synapses

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 62, Issue 1, 2015, Pages 215-223

  Adhikari, Shyam Prasad ^a   Kim, Hyongsuk ^a   Budhathoki, Ram Kaji ^a   Yang, Changju ^a   Chua, Leon O ^b  

^a Chonbuk National University   (South Korea)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Chip in the loop; memristor; memristor bridge synapse; neural learning hardware; neural network; random weight change

Indexed keywords

BACKPROPAGATION; MEMRISTORS; MULTILAYERS; NETWORK ARCHITECTURE; NEURAL NETWORKS; TIMING CIRCUITS;

CHIP-IN-THE-LOOP; CIRCUIT ARCHITECTURES; HARDWARE IMPLEMENTATIONS; LEARNING ARCHITECTURES; MEMRISTOR; NEURAL LEARNING; RANDOM WEIGHT; SIMPLE LEARNING ALGORITHMS;

MULTILAYER NEURAL NETWORKS;

EID: 84921409487     PISSN: 15498328     EISSN: 15580806     Source Type: Journal    
DOI: 10.1109/TCSI.2014.2359717     Document Type: Article

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