A thread-aware adaptive data prefetcher

2014 32nd IEEE International Conference on Computer Design, ICCD 2014

Volumn , Issue , 2014, Pages 278-285

  Yu, Jiyang ^a,b   Liu, Peng ^a,b  

^a ZHEJIANG UNIVERSITY   (China)

^b State Key Laboratory of Mathematical Engineering and Advanced Computing   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER HARDWARE; MEMORY ARCHITECTURE;

ENERGY DELAY PRODUCT; FILTERING MECHANISM; MEMORY ACCESS LATENCY; MULTI-CORE PROCESSOR; PERFORMANCE DEGRADATION; RESOURCE CONTENTION; RUN-TIME INFORMATION; SHARED RESOURCE CONTENTIONS;

DATA SHARING;

EID: 84919675365     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2014.6974694     Document Type: Conference Paper

References (25)

1. K. J. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith, "Fair queuing memory systems, " in Proc. Int'l Symp. on Microarch., Dec. 2006, pp. 208-222.
2. O. Mutlu and T. Moscibroda, "Parallelism-Aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems, " in Proc. Int'l Symp. on Comp. Arch., Jun. 2008, pp. 63-74.
3. Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter, "Thread cluster memory scheduling, " IEEE Micro, vol. 31, no. 1, pp. 78-89, Jan./Feb. 2011.
4. Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter, "ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers, " in Proc. Int'l Symp. on High Performance Comp. Arch., Jan. 2010, pp. 1-12.
5. S. Zhuravlev, S. Blagodurov, and A. Fedorova, "Addressing shared resource contention in multicore processors via scheduling, " in Proc. Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, Mar. 2010, pp. 129-142.
6. S. Zhuravlev, "AKULA: A toolset for experimenting and developing thread placement algorithms on multicore systems, " in Proc. Int'l Conf. on Parallel Arch. and Compilation Techniques, Sep. 2010, pp. 249-260.
7. A. Jaleel, H. H. Najaf-Abadi, S. Subramaniam, S. C. Steely, and J. Emer, "CRUISE: Cache replacement and utility-Aware scheduling, " in Proc. Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, Mar. 2012, pp. 249-260.
8. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt, "Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers, " in Proc. Int'l Symp. on High Performance Comp. Arch., Feb. 2007, pp. 63-74.
9. E. Ebrahimi, O. Mutlu, and Y. N. Patt, "Techniques for bandwidthefficient prefetching of linked data structures in hybrid prefetching systems, " in Proc. Int'l Symp. on High Performance Comp. Arch., Feb. 2009, pp. 7-17.
10. E. Ebrahimi, O. Mutlu, C. J. Lee, and Y. N. Patt, "Coordinated control of multiple prefetchers in multi-core systems, " in Proc. Int'l Symp. on Microarch., Dec. 2009, pp. 316-326.
11. E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Prefetch-Aware shared resource management for multi-core systems, " in Proc. Int'l Symp. on Comp. Arch., Dec. 2011, pp. 141-152.
12. C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC benchmark suite: Characterization and architectural implications, " in Proc. Int'l Conf. on Parallel Arch. and Compilation Techniques, Oct. 2008, pp. 72-81.
13. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations, " in Proc. Int'l Symp. on Comp. Arch., Jun. 1995, pp. 24-36.
14. R. Cooksey, S. Jourdan, and D. Grunwald, "A stateless, content-directed data prefetching mechanism, " in Proc. Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, Oct. 2002, pp. 279-290.
15. A. Roth, A. Moshovos, and G. S. Sohi, "Dependence based prefetching for linked data structures, " in Proc. Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, Oct. 1998, pp. 115-126.
16. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer, "Adaptive insertion policies for managing shared caches, " in Proc. Int'l Conf. on Parallel Arch. and Compilation Techniques, Oct. 2008, pp. 208-219.
17. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An infrastructure for computer system modeling, " Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
18. PoPNet, " http://www.princeton.edu/peh/orion.html.
19. MIPS Technologies, Inc., "MIPS32r 24KETM processor core family software user's manual, " Dec. 2008, Document Number: MD00468.
20. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures, " in Proc. Int'l Symp. on Microarch., Dec. 2009, pp. 469-480.
21. C. Sun, C.-H. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic, "DSENT: A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling, " in Proc. Int'l Symp. on Networks on Chip, May 2012, pp. 201-210.
22. N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-Associative cache and prefetch buffers, " in Proc. Int'l Symp. on Comp. Arch., May 1990, pp. 364-373.
23. S. Palacharla and R. E. Kessler, "Evaluating stream buffers as a secondary cache replacement, " in Proc. Int'l Symp. on Comp. Arch., Apr. 1994, pp. 24-33.
24. S. Iacobovici, L. Spracklen, S. Kadambi, Y. Chou, and S. G. Abraham, "Effective stream-based and execution-based data prefetching, " in Proc. Int'l Conf. on Supercomputing, Jun. 2004, pp. 1-11.
25. J. W. C. Fu, J. H. Patel, and B. L. Janssens, "Stride directed prefetching in scalar processors, " in Proc. Int'l Symp. on Microarch., Dec. 1992, pp. 102-110.