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Volumn , Issue , 2014, Pages 1-12

Unifying on-chip and inter-node switching within the Anton 2 network

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DESIGN; EMBEDDED SYSTEMS; INVERSE PROBLEMS; MOLECULAR DYNAMICS; NETWORK ARCHITECTURE; ROUTERS; ROUTING ALGORITHMS; SUPERCOMPUTERS;

EID: 84905474716     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2014.6853238     Document Type: Conference Paper
Times cited : (35)

References (29)
  • 6
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm"Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 7
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip"ACM Computing Surveys, vol. 38, no. 1, 2006
    • (2006) ACM Computing Surveys , vol.38 , Issue.1
    • Bjerregaard, T.1    Mahadevan, S.2
  • 9
    • 33746286995 scopus 로고    scopus 로고
    • Principles and practices of interconnection networks san francisco
    • W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann Publishers Inc., 2003
    • (2003) Morgan Kaufmann Publishers Inc
    • Dally, W.1    Towles, B.2
  • 10
    • 0025448089 scopus 로고
    • Performance analysis of k-Ary n-cube interconnection networks
    • W. Dally, "Performance analysis of k-Ary n-cube interconnection networks"IEEE Transactions on Computers, vol. 39, no. 6, pp. 775-785, 1990
    • (1990) IEEE Transactions on Computers , vol.39 , Issue.6 , pp. 775-785
    • Dally, W.1
  • 11
    • 0023346637 scopus 로고
    • Deadlock-free message routing in multiprocessor interconnection networks
    • W. Dally and C. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks"IEEE Transactions on Computers, vol. 36, no. 5, pp. 547-553, 1987
    • (1987) IEEE Transactions on Computers , vol.36 , Issue.5 , pp. 547-553
    • Dally, W.1    Seitz, C.2
  • 17
    • 24144490066 scopus 로고    scopus 로고
    • Designing and implementing a fast crossbar scheduler
    • P. Gupta and N. McKeown, "Designing and implementing a fast crossbar scheduler"IEEE Micro, vol. 19, no. 1, pp. 20-28, 1999
    • (1999) IEEE Micro , vol.19 , Issue.1 , pp. 20-28
    • Gupta, P.1    McKeown, N.2
  • 22
    • 36849063126 scopus 로고    scopus 로고
    • Research challenges for on-chip interconnection networks
    • J. Owens, W. Dally, R. Ho, D. N. Jayasimha, S. Keckler, and L.-S. Peh, "Research challenges for on-chip interconnection networks"IEEE Micro, vol. 27, no. 5, pp. 96-108, 2007
    • (2007) IEEE Micro , vol.27 , Issue.5 , pp. 96-108
    • Owens, J.1    Dally, W.2    Ho, R.3    Jayasimha, D.N.4    Keckler, S.5    Peh, L.-S.6
  • 26
    • 84905509507 scopus 로고    scopus 로고
    • TSMC first to deliver 40nm process technology Mar
    • Taiwan Semiconductor Manufacturing Company (TSMC), "TSMC first to deliver 40nm process technology"Mar. 2008. Available: http://www.tsmc.com/ tsmcdotcom/PRListingNewsAction.do? action=detail&newsid=2561
    • (2008) Taiwan Semiconductor Manufacturing Company (TSMC)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.