Unifying on-chip and inter-node switching within the Anton 2 network

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2014, Pages 1-12

  Towles, Brian ^a   Grossman, J P ^a   Greskamp, Brian ^a   Shaw, David E ^a,b  

^a D E SHAW RESEARCH   (United States)

^b Howard Hughes Medical Institute   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DESIGN; EMBEDDED SYSTEMS; INVERSE PROBLEMS; MOLECULAR DYNAMICS; NETWORK ARCHITECTURE; ROUTERS; ROUTING ALGORITHMS; SUPERCOMPUTERS;

DEADLOCK-FREE ROUTING ALGORITHMS; DESIGN CHALLENGES; DISTRIBUTED SYSTEMS; IMPLEMENTATION COST; MASSIVELY PARALLELS; MOLECULAR DYNAMICS SIMULATIONS; OPTIMIZATION APPROACH; ROUTING DECISIONS;

COMPLEX NETWORKS;

EID: 84905474716     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2014.6853238     Document Type: Conference Paper

References (29)

1. D. Abts and D. Weisser, "Age-based packet arbitration in large-radix k-Ary n-cubes"in Proceedings of the 2007 ACM/IEEE conference on Supercomputing (SC), Nov. 2007, pp. 1-11
2. A. Agarwal, "Limits on interconnection network performance"IEEE Transactions on Parallel and Distributed Systems, vol. 2, no. 4, pp. 398-412, 1991
3. B. Alverson, "Cray high speed networking"in Proceedings of the 20th Annual Symposium on High-Performance Interconnects (HOTI), Aug. 2012
4. J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks"in Proceedings of the 20th annual International Conference on Supercomputing (ICS), Jun. 2006, pp. 187-198
5. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "TILE64 processor: A 64-core SoC with mesh interconnect"in Proceedings of the International Solid-State Circuits Conference (ISSCC), Feb. 2008, pp. 88-89, 598
6. L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm"Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002
7. T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip"ACM Computing Surveys, vol. 38, no. 1, 2006
8. G. Chrysos, "IntelR Xeon PhiTM coprocessor (codename Knights Corner)"in Proceedings of the 24th Annual IEEE Hot Chips Symposium, 2012
9. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann Publishers Inc., 2003
10. W. Dally, "Performance analysis of k-Ary n-cube interconnection networks"IEEE Transactions on Computers, vol. 39, no. 6, pp. 775-785, 1990
11. W. Dally and C. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks"IEEE Transactions on Computers, vol. 36, no. 5, pp. 547-553, 1987
12. E. DeLano, "Tukwila-A quad-core IntelR ItaniumR processor"in Proceedings of the 20th Annual IEEE Hot Chips Symposium, 2012
13. R. O. Dror, J. P. Grossman, K. M. Mackenzie, B. Towles, E. Chow, J. K. Salmon, C. Young, J. A. Bank, B. Batson, M. M. Deneroff, J. S. Kuskin, R. H. Larson, M. A. Moraes, and D. E. Shaw, "Exploiting 162-nanosecond end-to-end communication latency on Anton"in Proceedings of the Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2010, pp. 1-12
14. N. Eisley and L.-S. Peh, "High-level power analysis for on-chip networks"in Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Sep. 2004, pp. 104-115
15. J. P. Grossman, J. S. Kuskin, J. A. Bank, M. Theobald, R. O. Dror, D. J. Ierardi, R. H. Larson, U. B. Schafer, B. Towles, C. Young, and D. E. Shaw, "Hardware support for fine-grained event-driven computation in Anton 2"in Proceedings of the 18th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr. 2013, pp. 549-560
16. B. Grot, S. Keckler, and O. Mutlu, "Preemptive virtual clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip"in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2009, pp. 268-279
17. P. Gupta and N. McKeown, "Designing and implementing a fast crossbar scheduler"IEEE Micro, vol. 19, no. 1, pp. 20-28, 1999
18. J. Lee, M. C. Ng, and K. Asanovíc, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks"in Proceedings of the 35th annual International Symposium on Computer Architecture (ISCA), Jun. 2008, pp. 89-100
19. M. M. Lee, J. Kim, D. Abts, M. Marty, and J. W. Lee, "Probabilistic distance-based arbitration: providing equality of service for many-core CMPs"in Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2010, pp. 509-519
20. T. Nesson and S. L. Johnsson, "ROMM routing on mesh and torus networks"in Proceedings of the 7th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA), Jul. 1995, pp. 275-287
21. T. D. Nguyen and L. Snyder, "Performance analysis of a minimal adaptive router"in Parallel Computer Routing and Communication: 1st International Workshop (PCRCW), May 1994, pp. 31-44
22. J. Owens, W. Dally, R. Ho, D. N. Jayasimha, S. Keckler, and L.-S. Peh, "Research challenges for on-chip interconnection networks"IEEE Micro, vol. 27, no. 5, pp. 96-108, 2007
23. S. Scott and G. Thorson, "The Cray T3E network: Adaptive routing in a high performance 3D torus"in Proceedings of the 4th Annual Symposium on High-Performance Interconnects (HOTI), Aug. 1996
24. D. E. Shaw, R. O. Dror, J. K. Salmon, J. P. Grossman, K. M. Mackenzie, J. A. Bank, C. Young, M. M. Deneroff, B. Batson, K. J. Bowers, E. Chow, M. P. Eastwood, D. J. Ierardi, J. L. Klepeis, J. S. Kuskin, R. H. Larson, K. Lindorff-Larsen, P. Maragakis, M. A. Moraes, S. Piana, Y. Shan, and B. Towles, "Millisecond-scale molecular dynamics simulations on Anton"in Proceedings of the Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009, pp. 1-11
25. A. Singh,W. J. Dally, B. Towles, and A. K. Gupta, "Locality- preserving randomized oblivious routing on torus networks"in Proceedings of the 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA), Aug. 2002, pp. 9-13
26. Taiwan Semiconductor Manufacturing Company (TSMC), "TSMC first to deliver 40nm process technology"Mar. 2008. Available: http://www.tsmc.com/ tsmcdotcom/PRListingNewsAction.do? action=detail&newsid=2561
27. B. Towles and W. J. Dally, "Worst-case traffic for oblivious routing functions"in Proceedings of the 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA), Aug. 2002, pp. 1-8
28. L. G. Valiant and G. J. Brebner, "Universal schemes for parallel communication"in Proceedings of the Thirteenth Annual ACM Symposium on Theory of Computing (STOC), May 1981, pp. 263-277
29. H. Wang, L.-S. Peh, and S. Malik, "A technology-Aware and energyoriented topology exploration for on-chip networks"in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Mar. 2005, pp. 1238-1243.