Full-system simulation from embedded to high-performance systems

Processor and System-on-Chip Simulation

Volumn , Issue , 2010, Pages 25-45

  Engblom, Jakob ^a,b   Aarno, Daniel ^b   Werner, Bengt ^b  

^a Wind River   (Sweden)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84867497756     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4419-6175-4_3     Document Type: Chapter

References (16)

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4. Engblom, J.: System architecture specification and exploration using a full-system simulator. Virtutech Whitepaper (2009).
5. Rosenblum, M., Varadarajan, M.: Simos: A fast operating system simulation environment. Technical Report CSL-TR-94-631, Stanford University (1994).
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7. Engblom, J.: Why virtual platforms need cycle-accurate models. SCDSource (2008).
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9. Albertsson, L.: "Holistic debugging-enabling instruction set simulation for software quality assurance." In: Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS) Monterrey, California, USA, September 11-14 (2006).
10. Stetter, M., Von Buttlar, J., Chan, P. T., Decker, D., Elfering, H., Giquindo, P. M., Hess, T., Koerner, S., Kohler, A., Lindner, H., Petri, K., Zee, M.: IBM eserver z990 improvements in firmware simulation. IBM J Res Dev 48:583-594 (2004).
11. Aynsley, J.: OSCI TLM-2.0 Language Reference Manual. Open SystemC Initiative (OSCI) (2009).
12. Engblom, J., Monton, M., Burton, M.: Checkpoint and restore for systemc models. In: Forum on Specification and Design Languages (FDL) France, September 22-24 (2009).
13. Kraemer, S., Leupers, R., Petras, D., Philipp, T.: A checkpoint/restore framework for systemc-based virtual platforms. In: International Symposium on System-on-Chip (SoC) pp. 161-167, Tampere, Finland, October 5-7 (2009).
14. Koerner, S., Kohler, A., Babinsky, J., Pape, H., Eickhoff, F., Kriese, S., Elfering, H.: Ibm system z10 firmware simulation. IBM J Res Dev 53 (2009).
15. Fuchi, K., Tanaka, H., Manago, Y., Yuba, T.: A program simulator by partial interpretation. In: SOSP'69: Proceedings of the Second Symposium on Operating Systems Principles, Princeton, NJ, USA, October 20-22, pp. 97-104 (1969).
16. Cornet, J., Maraninchi, F., Maillet-Contoz, L.: "A method for the efficient development of timed and untimed transaction-level models of systems-on-chip. " In: DATE'08: Proceedings of the Conference on Design, Automation and Test in Europe, München, Germany, March 10-14, pp. 9-14 (2008). DOI http://doi.acm.org/10.1145/1403375.1403381.