Synthesis of processor instruction sets from high-level ISA specifications

IEEE Transactions on Computers

Volumn 63, Issue 6, 2014, Pages 1552-1566

  Mokhov, Andrey ^a   Iliasov, Alexei ^a   Sokolov, Danil ^a   Rykunov, Maxim ^a   Yakovlev, Alex ^a   Romanovsky, Alexander ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

instruction set; Microprocessor; synthesis

Indexed keywords

ENERGY EFFICIENCY; FORMAL SPECIFICATION; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; SYNTHESIS (CHEMICAL);

8051 MICROCONTROLLERS; FORMAL SPECIFICATION AND VERIFICATION; HARDWARE RESOURCES; HIGH-LEVEL DESIGN; INSTRUCTION SET; INSTRUCTION SET ARCHITECTURE; MODELLING FRAMEWORK; SOFTWARE REQUIREMENTS;

COMPUTER ARCHITECTURE;

EID: 84903175612     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2013.37     Document Type: Article

References (40)

1. Dalton project 8051controller [Online]. Available: http://www.cs.ucr. edu/?dalton/i8051.
2. Opencores.org 8051core Project [Online]. Available: http://opencores. org/project,8051.
3. Oregano Systems 8051core [Online]. Available: http://www.oreganosystems. at/?page-id=172.
4. (2009). International Technology Roadmap for Semiconductors: Design [Online]. Available: http://www.itrs.net/Links/2009ITRS/Home 2009.htm.
5. Newcastle University (2009). The Workcraft Framework Homepage [Online]. Available: http://www.workcraft.org.
6. Newcastle University (2012). The RODINToolset [Online]. Available: http://www.rodintools.org.
7. J.-R. Abrial, Modelling in Event-B. Cambridge, U.K.: Cambridge Univ. Press, 2010.
8. H. H. Aiken and G. M. Hopper, "The automatic sequence controlled calculator,"Electr.Eng.,vol.65,no.8-9,pp.384-391;no.10,pp.449-454; no. 11, pp. 522-528, Nov. 1946.
9. S. Baranov, Logic Synthesis for Control Automata. Norwell, MA: Kluwer, 1994.
10. G. Birkhoff, Lattice Theory, 3rd ed. Providence, RI: American Mathematical Society, 1967.
11. P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh, "Instruction generation and regularity extraction for reconfigurable processors," in Proc. Int. Conf. Compilers, Archit., Synth. Embedded Syst. (CASES), 2002, pp. 262-269.
12. P. Brisk, A. Kaplan, and M. Sarrafzadeh. "Area-efficient instruction set synthesis for reconfigurable system-on-chip designs," in Proc. 41st Des. Autom. Conf. (DAC), 2004, pp. 395-400.
13. A. Bundy, A. Stevens, F. van Harmelen, A. Ireland, and A. Smaill, "Rippling: A heuristic for guiding inductive proofs," Artif. Intell., vol. 62, no. 2, pp. 185-253, 1993. (Pubitemid 23698136)
14. D. Cansell, D. Mery, and C. Proch, "System-on-chip design by proof-based refinement," Int. J. Softw. Tools Tech. Transfer, vol. 11, pp. 217-238, 2009.
15. N. Clark, H. Zhong, and S. A. Mahlke, "Processor acceleration through automated instruction set customization," in Proc. IEEE/ACM Int. Symp. Microarchit. (MICRO), 2003, pp. 129-140.
16. J. Cocke and V. Markstein, "The evolution of RISC technology at IBM," IBM J. Res. Dev., vol. 44, pp. 48-55, Jan. 2000.
17. J. Colley, Guarded atomic actions and refinement in a system-onchip development flow: Bridging the specification gap with event-B. Ph.D. dissertation, School of Electronics and Computer Science, Univ. Southampton, Southampton, U.K., 2010.
18. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces. New York, NY: Springer-Verlag, 2002.
19. J. A. Fisher, "Very long instruction word architectures and the eli-512," SIGARCH Comput. Archit. News, vol. 11, pp. 140-150, Jun. 1983.
20. A. Fox and M. Myreen, "A trustworthy monadic formalization of the ARMv7 instruction set architecture," in Proc. Interact. Theorem Proving (ITP), 2010, pp. 243-258.
21. S. Furber,ARMSystem-on-ChipArchitecture, 2nd ed. Boston:Addison-Wesley Longman Publishing Co., Inc., 2000.
22. R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis, and M. Horowitz, "Understanding sources of inefficency in general-purpose chips," Commun. ACM, vol. 54, no. 10, pp. 85-93, 2011.
23. J. Harrison, "Formal verification of IA-64 division algorithms," in Proc. Theorem Prov. Higher Order Logics (TPHOLs), 2000, pp 234-251.
24. S. Heath, Microprocessor Architectures RISC, CISC, and DSP, 2nd ed. Oxford, U.K.: Butterworth-Heinemann Ltd., 1995.
25. A. Iliasov, "Use case scenarios as verification conditions: Event-B/Flow approach," in Proc. 3rd Int. Workshop Softw. Eng. Resilient Syst., Sep. 2011, pp. 9-23.
26. D. Knuth, MMIXware,ARISC Computer for the Third Millennium. vol. 1750, New York, NY: Springer-Verlag, 1999.
27. J.-E. Lee, K. Choi, and N. Dutt, "Energy-efficient instruction set synthesis for application-specific processors," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED), 2003, pp. 330-333.
28. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York, NY: McGraw-Hill, 1994.
29. A. Mokhov, "Conditional partial order graphs," Ph.D. dissertation, School of Electrical and Electronic Engineering, Newcastle Univ., Newcastle, U.K., 2009.
30. A. Mokhov, A. Alekseyev, and A. Yakovlev, "Encoding of processor instruction sets with explicit concurrency control," IET Comput. Digit. Techn., vol. 5, no. 6, pp. 427-439, 2011.
31. A. Mokhov, D. Sokolov, M. Rykunov, and A. Yakovlev, "Formal modelling and transformations of processor instruction sets," in Int. Conf. Formal Methods Models Codes. (MEMOCODE), 2011, pp. 51-60.
32. A. Mokhov and A. Yakovlev, "Conditional partial order graphs: Model, synthesis and application," IEEE Trans. Comput., vol. 59, no. 11, pp. 1480-1493, 2010.
33. M. O. Myreen, "Verified just-in-time compiler on x86," in M. V. Hermenegildo and J. Palsberg, Eds. Proc. Princ. Programm. Lang. (POPL), 2010, pp. 107-118.
34. N. Pothineni, P. Brisk, P. Ienne, A. Kumar, and K. Paul, "Ahigh-level synthesis flow for custom instruction set extensions for applicationspecific processors," in Proc. Asia South Pacific Des. Autom. Conf. (ASPDAC), 2010, pp. 707-712.
35. D. Sokolov and A. Yakovlev, "Task scheduling based on energy token model," in Workshop Micro Power Manage. Macro Syst. Chip (uPM2SoC), 2011, pp. 4-6.
36. C. Steiner, The 8051/8052 Microcontroller: Architecture, Assembly Language, and Hardware Interfacing. Florida: Universal Publishers, 2005.
37. J. Van Praet, G. Goossens, D. Lanneer, and H. De Man, "Instruction set definition and instruction selection for ASIPs," in Proc. Int. Symp. High-Level Synth., 1994, pp. 11-16.
38. F. Xia, A. Mokhov, Y. Zhou, Y. Chen, I. Mitrani, D. Shang, D. Sokolov, and A. Yakovlev, "Towards power-elastic systems through concurrency management," IET Comput. Digit. Techn., vol. 6, no. 1, pp. 33-42, 2012.
39. F. Yuan and K. Eder, "Ageneric instruction set architecture model in event-B for early design space exploration," Tech. Rep. CSTR-09-006, Univ. Bristol, Bristol, U.K., Sep. 2009.
40. F. Yuan, S. Wright, K. Eder, and D. May, "Managing complexity through abstraction: A refinement-based approach to formalize instruction set architectures," in 13th Int. Conf. Formal Eng. Methods, 2011, pp. 585-600.