A 0.45 v 100-channel neural-recording IC with sub-μW/Channel Consumption in 0.18 μ CMOS

IEEE Transactions on Biomedical Circuits and Systems

Volumn 7, Issue 6, 2013, Pages

  Han, Dong ^a   Zheng, Yuanjin ^b   Rajkumar, Ramamoorthy ^a   Dawe, Gavin Stewart ^a,c,d,e   Je, Minkyu ^b,d  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^d NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^e SINAPSE Singapore Institute for Neurotechnology   (Singapore)

Author keywords

Current reuse; dynamic range folding; multichannel neural recording; noise efficiency factor (NEF); successive approximation register (SAR); two level power supply

Indexed keywords

CURRENT REUSE; DYNAMIC RANGE; NEURAL RECORDINGS; NOISE EFFICIENCY FACTORS; POWER SUPPLY; SUCCESSIVE APPROXIMATION REGISTER;

SENSORS;

NEUROPHYSIOLOGY;

SILICON;

ANIMAL; ARTICLE; ELECTRODE IMPLANT; EQUIPMENT; EQUIPMENT DESIGN; MICROELECTROMECHANICAL SYSTEM; NEUROLOGIC EXAMINATION; NEUROPROSTHESIS; RAT; SEMICONDUCTOR; SIGNAL PROCESSING; SPRAGUE DAWLEY RAT;

ANIMALS; DIAGNOSTIC TECHNIQUES, NEUROLOGICAL; ELECTRODES, IMPLANTED; EQUIPMENT DESIGN; MICRO-ELECTRICAL-MECHANICAL SYSTEMS; NEURAL PROSTHESES; RATS; RATS, SPRAGUE-DAWLEY; SEMICONDUCTORS; SIGNAL PROCESSING, COMPUTER-ASSISTED; SILICON;

EID: 84893820774     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2014.2298860     Document Type: Article

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