A 90 nm low-power successive approximation register for A/D conversions

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Volumn , Issue , 2011, Pages 311-315

  Shaker, Mohamed O ^a   Bayoumi, Magdy A ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

clock gating; layout simulations; Low power; successive approximation register

Indexed keywords

90NM CMOS; A/D CONVERSION; CLOCK GATING; LAYOUT SIMULATIONS; LOW POWER; LOW POWER APPLICATION; POWER SUPPLY; SIMULATION RESULT; SUCCESSIVE APPROXIMATION REGISTER; SWITCHING ACTIVITIES; TRANSISTOR COUNT;

CMOS INTEGRATED CIRCUITS;

APPROXIMATION THEORY;

EID: 79959275845     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770742     Document Type: Conference Paper

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