Controlled timing-error acceptance for low energy IDCT design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 758-763

  He, Ku ^a   Gerstlauer, Andreas ^a   Orshansky, Michael ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL LOGIC; DIGITAL DESIGNS; ENERGY SAVING; LOSSY IMAGES; LOW ENERGIES; ORIGINAL DESIGN; PEAK SIGNAL-TO-NOISE RATIO; PRACTICAL SYSTEMS; SIGNAL TO NOISE; STANDARD CELL; TIMING ERRORS; VIDEO COMPRESSION;

ELECTRIC BATTERIES; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; IMAGE COMPRESSION; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

DESIGN;

EID: 79957542209     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. S. H. Nawab, A. V. Oppenheim, A. P. Chandrakasan, J. M. Winograd, and J. T. Ludwig, "Approximate signal processing," VLSI Signal Processing, vol. 15, pp. 177-200, 1997.
2. J. T. Ludwig, S. H. Nawab, and A. P. Chandrakasan, "Low-power digital filtering using approximate processing," JSSC, pp. 395-400, 1996.
3. A. Sinha and A. P. Chandraksan, "Energy efficient filtering using adaptive precision and variable voltage," ASIC SOC Conference, pp. 327-331, 1999.
4. R. Hedge and N. R. Shanbhag, "Soft digital signal processing," TVLSIS, pp. 379-391, 2000.
5. L. Wang and N. R. Shanbhag, "Low-power filtering via adaptive error-cancellation," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 51, no. 2, pp. 575-583, 2003.
6. J. Park, S. Kwon, and K. Roy, "Low power reconfigurable dct design based on sharing multiplication," ICASSP, pp. III-3116-III-3119, 2002.
7. G. Karakonstantis, D. Mohapatra, and K. Roy, "System level dsp synthesis using voltage overscaling, unequal error protection and adaptive quality tuning," SIPS, 2009.
8. N. Banerjee, G. Karakonstantis, and K. Roy, "Process variation tolerant low power dct artchitecture," DATE, pp. 1-6, 2007.
9. E. Y. Lam and J. W. Goodman, "A mathematical analysis of the dct coefficient distribution for images," IEEE transaction on image processing, vol. 9, no. 10, pp. 1661-1666, 2000.
10. S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, and Y. Yamashita, "A 100-mhz 2-d discrete cosine transform core processor," JSSC, vol. 27, pp. 492-499, 1992.