Design and evaluation of reduced self-capacitance inductor in DC/DC converters with fast-switching SiC transistors

IEEE Transactions on Power Electronics

Volumn 29, Issue 5, 2014, Pages 2492-2499

  Zdanowski, Mariusz ^a   Kostov, Konstantin ^b   Rabkowski, Jacek ^a,b   Barlik, Roman ^a   Nee, Hans Peter ^b  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Electromagnetic interference; inductors; junction field effect transistors (JFETs); parasitic capacitance; silicon carbide (SiC)

Indexed keywords

CAPACITANCE; ELECTRIC INDUCTORS; ELECTRIC INVERTERS; ELECTROMAGNETIC PULSE; JUNCTION GATE FIELD EFFECT TRANSISTORS; POWER BIPOLAR TRANSISTORS; SIGNAL INTERFERENCE; SILICON CARBIDE; TRANSISTORS;

DESIGN AND EVALUATIONS; ELECTROMAGNETIC EMISSIONS; JUNCTION FIELD EFFECT TRANSISTORS; JUNCTION FIELD-EFFECT TRANSISTORS (JFETS); PARASITIC CAPACITANCE; SELF-CAPACITANCE; SILICON CARBIDES (SIC); SWITCHING PERFORMANCE;

DC-DC CONVERTERS;

EID: 84893052013     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2013.2281990     Document Type: Article

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