Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

2013 IEEE 31st International Conference on Computer Design, ICCD 2013

Volumn , Issue , 2013, Pages 123-130

  Cai, Yu ^a   Mutlu, Onur ^a   Haratsch, Erich F ^b   Mai, Ken ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

error correction; error model; NAND flash; program interference; read retry; reliability

Indexed keywords

CHARACTERIZATION; DESIGN; ERROR CORRECTION; FLASH MEMORY; NAND CIRCUITS; RELIABILITY; THRESHOLD VOLTAGE; VOLTAGE DISTRIBUTION MEASUREMENT; VOLTAGE DIVIDERS;

ERROR MODEL; EXPERIMENTAL CHARACTERIZATION; NAND FLASH; NAND FLASH MEMORY; PROCESS TECHNOLOGIES; READ RETRY; REFERENCE VOLTAGES; THRESHOLD VOLTAGE DISTRIBUTION;

INTERFERENCE SUPPRESSION;

EID: 84892550593     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2013.6657034     Document Type: Conference Paper

References (17)

1. J. Seo et al., "A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies", IEDM 2011.
2. K.-D. Suh et al., "A 3.3V 32 Mb NAND flash memory with incremental step pulse programming scheme", JSSC 1995.
3. K. Park et al. "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", JSSC 2008.
4. J. Lee et al. "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation", IEEE EDL 2002.
5. G. Dong et al. "Using Data Postcompensation and Prediction to Tolerate Cell-to-Cell Interference in MLC NAND Flash Memory", IEEE TCAS- I, 2010.
6. D. Park et al. "Floating-gate coupling canceller for multi-level cell NAND flash", IEEE Transactions on Magnetics, 2011.
7. D. Lee et al. "Least squares based cell-to-cell interference cancelation technique for multi-level cell NAND flash memory", ICASSP 2012.
8. Y. Cai et al. "Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling", DATE 2013.
9. Y. Cai et al. "FPGA-Based Solid-State Drive Prototyping Platform", FCCM 2011.
10. T. Hara et al., "A 146 mm2 8 Gb NAND flash memory with 70 nm technology," ISSCC 2005.
11. R. Cernea et al., "A 32 MB/s MLC Write Throughput 16 Gb NAND with All Bit Line Architecture on 56 nm Technology", JSSC 2009.
12. Y. Cai et al. "Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime", ICCD 2012.
13. C. Lee et al. "A 32-Gb MLC NAND flash memory with Vth endurance enhancing in 32nm CMOS", JSSC 2011.
14. R. Tibshirani, "Regression shrinkage and selection via the LASSO", Technical report, University of Toronto, 1994.
15. Y. Cai et al., "Error patterns in MLC NAND flash memory: measurement, characterization and analysis", DATE 2012.
16. N. Mielke et al., "Bit error rate in NAND flash memories", IEEE RPS, 2008.
17. Y. Cai et al., "Error analysis and retention-aware error management for NAND flash memory", Intel Technology Journal (ITJ), 2013.