Least squares based cell-to-cell interference cancelation technique for multi-level cell nand flash memory

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn , Issue , 2012, Pages 1601-1604

  Lee, Dong Hwan ^a   Sung, Wonyong ^a  

^a Seoul National University   (South Korea)

Author keywords

Cell to cell interference; least squares; LMS adaptive filter; NAND flash memory

Indexed keywords

BIT-ERRORS; CHANNEL CHARACTERISTICS; INPUT DATAS; LEAST MEAN SQUARES; LEAST SQUARE; LMS ADAPTIVE FILTERS; MULTILEVEL CELL; NAND FLASH MEMORY; PROCESSING APPROACH; SEMICONDUCTOR TECHNOLOGY; SIMULATION MODEL;

ADAPTIVE FILTERS; ALGORITHMS; CELLS; COMPUTER SIMULATION; LEAST SQUARES APPROXIMATIONS; NAND CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SIGNAL PROCESSING;

CYTOLOGY;

EID: 84867614372     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2012.6288200     Document Type: Conference Paper

References (8)

1. D. Park and J. Lee, "Floating-gate coupling canceller for multi-level cell NAND flash," IEEE Transactions on Magnetics, vol. 47, no. 3, pp. 624-628, 2011.
2. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, 2003.
3. J.D. Lee, S.H. Hur, and J.D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Letters, vol. 23, no. 5, pp. 264-266, 2002.
4. K. Prall, "Scaling non-volatile memory below 30nm," in Proceedings of 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007, pp. 5-10.
5. R.A. Cernea, L. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T.Y. Tseng, K. Nguyen, J. Li, et al., "A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology," IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 186-194, 2009.
6. K.T. Park, M. Kang, D. Kim, S.W. Hwang, B.Y. Choi, Y.T. Lee, C. Kim, and K. Kim, "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 919-928, 2008.
7. G. Dong, S. Li, and T. Zhang, "Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2718-2728, 2010.
8. K.D. Suh, B.H. Suh, Y.H. Lim, J.K. Kim, Y.J. Choi, Y.N. Koh, S.S. Lee, S.C. Kwon, B.S. Choi, J.S. Yum, et al., "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, 1995.