C-pack: A high-performance microprocessor cache compression algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 8, 2010, Pages 1196-1208

  Chen, Xi ^a   Yang, Lei ^b   Dick, Robert P ^a   Shang, Li ^c   Lekatsas, Haris ^d  

^a UNIVERSITY OF MICHIGAN   (United States)

^b GOOGLE INC   (United States)

^c University of Colorado at Boulder   (United States)

^d Vorras Corporation   (United States)

Author keywords

Cache compression; effective system wide compression ratio; hardware implementation; pair matching; parallel compression

Indexed keywords

AREA ESTIMATION; AREA OVERHEAD; COMPRESSION ALGORITHMS; COMPRESSION RATIOS; DYNAMIC RANDOM ACCESS MEMORY; HARDWARE DESIGN; HARDWARE IMPLEMENTATIONS; HIGH-PERFORMANCE MICROPROCESSORS; LOSSLESS COMPRESSION ALGORITHM; MEMORY HIERARCHY; MICRO ARCHITECTURES; OFF-CHIP MEMORIES; ON-CHIP CACHE; ONLINE DATA; ORDER OF MAGNITUDE; ORDERS OF MAGNITUDE; PAIR MATCHING; POWER CONSUMPTION; REGISTER TRANSFER LEVEL;

ALGORITHMS; CACHE MEMORY; COMPUTER HARDWARE; ENERGY EFFICIENCY; HARDWARE; IMAGE COMPRESSION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; RANDOM ACCESS STORAGE;

DATA COMPRESSION;

EID: 77955170824     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2020989     Document Type: Article

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