Buffer-on-board memory systems

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 392-403

  Cooper Balis, Elliott ^a   Rosenfeld, Paul ^a   Jacob, Bruce ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL LOGIC; CAPACITY LIMITATION; CLOCK RATE; DESIGN SPACES; FABRICATION COST; FULL-SYSTEM SIMULATION; GENERAL APPROACH; IMPLEMENTATION COST; INTERMEDIATE LOGIC; MAPPING SCHEME; MEMORY SYSTEMS; NON-TRIVIAL; OPTIMAL PERFORMANCE; SIGNAL INTEGRITY;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DESIGN; OPTIMIZATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84864831405     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237034     Document Type: Conference Paper

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