-
1
-
-
0036149420
-
Network on chips: A new soc paradigm
-
January
-
L. Benini and G. D. Micheli. Network on Chips: A New SoC Paradigm. IEEE Computer, 35(1):70-78, January 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
2
-
-
84941344008
-
Interfacing cores with on-chip packet-switched networks
-
January
-
P. Bhojwani and R. Mahapatra. Interfacing Cores with On-chip Packet-Switched Networks. In IEEE Proceedings on VLSI Design, pages 382-387, January 2003.
-
(2003)
IEEE Proceedings on VLSI Design
, pp. 382-387
-
-
Bhojwani, P.1
Mahapatra, R.2
-
4
-
-
0345855761
-
Layered, multithreaded, high-level performance design
-
March
-
A. S. Cassidy, J. M. Paul, and D. E. Thomas. Layered, MultiThreaded, High-Level Performance Design. In Design Automation and Test in Europe, DATE, pages 954-959, March 2003.
-
(2003)
Design Automation and Test in Europe, DATE
, pp. 954-959
-
-
Cassidy, A.S.1
Paul, J.M.2
Thomas, D.E.3
-
8
-
-
0031097394
-
Design of embedded systems: Formal models validation and synthesis
-
March
-
S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models, Validation, and Synthesis. Proceedings of the IEEE, 85(3):366-390, March 1997.
-
(1997)
Proceedings of the IEEE
, vol.85
, Issue.3
, pp. 366-390
-
-
Edwards, S.1
Lavagno, L.2
Lee, E.A.3
Sangiovanni-Vincentelli, A.4
-
11
-
-
84893687806
-
A generic architecture for on-chip packet-switched interconnections
-
March
-
P. Guerrier and A. Greiner. A Generic Architecture for On-Chip Packet-Switched Interconnections. In Design Automation and Test in Europe, DATE, pages 250-256, March 2000.
-
(2000)
Design Automation and Test in Europe, DATE
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
12
-
-
33646922057
-
The future of wires
-
April
-
R. Ho and K. W. Mai. The Future of Wires. Proceedings of the IEEE, 89(4):490-504, April 2001.
-
(2001)
Proceedings of the IEEE
, vol.89
, Issue.4
, pp. 490-504
-
-
Ho, R.1
Mai, K.W.2
-
15
-
-
84948696213
-
A network-on-chip architecture and design methodology
-
April
-
S. Kumar, A. Jantsch, J-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A Network-on-Chip Architecture and Design Methodology. In IEEE Computer Society Annual Symposium on VLSI, pages 117-124, April 2002.
-
(2002)
IEEE Computer Society Annual Symposium on VLSI
, pp. 117-124
-
-
Kumar, S.1
Jantsch, A.2
Soininen, J.-P.3
Forsell, M.4
Millberg, M.5
Oberg, J.6
Tiensyrja, K.7
Hemani, A.8
-
16
-
-
0034273528
-
What's ahead for embedded software?
-
September
-
E. A. Lee. What's Ahead for Embedded Software? IEEE Computer, 33(9):18-26, September 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.9
, pp. 18-26
-
-
Lee, E.A.1
-
21
-
-
0036858279
-
A hardware-software real-time operating system framework for SoC's
-
Nov/Dec
-
V. J. Mooney and D. M. Blough. A Hardware-Software Real-Time Operating System Framework for SoC's. IEEE Design & Test of Computers, 19(6):44-51, Nov/Dec 2002.
-
(2002)
IEEE Design & Test of Computers
, vol.19
, Issue.6
, pp. 44-51
-
-
Mooney, V.J.1
Blough, D.M.2
-
22
-
-
84891377964
-
-
SystemC Workgroup
-
SystemC Workgroup. http://www.systemc.org.
-
-
-
-
23
-
-
84891477420
-
Resource allocation model for modelling abstract rtos on multiprocessor system-on-chip
-
November
-
K. Virk and J. Madsen. Resource Allocation Model for Modelling Abstract RTOS on Multiprocessor System-on-Chip. In The 21st Norchip Conference, November 2003.
-
(2003)
The 21st Norchip Conference
-
-
Virk, K.1
Madsen, J.2
|