The state-of-the-art in IC reverse engineering

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5747 LNCS, Issue , 2009, Pages 363-381

  Torrance, Randy ^a   James, Dick ^a  

^a Chipworks Inc   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BACK UP; CIRCUIT EXTRACTION; HARDWARE AND SOFTWARE; IN-CHIP; INTEGRATION LEVELS; MOORE'S LAW; PROCESS ANALYSIS; REVERSE ENGINEERS; SEMICONDUCTOR INDUSTRY; SEMICONDUCTOR PRODUCTS; SILICON CHIP; SYSTEM-LEVEL ANALYSIS; TECHNIQUES USED; TRANSISTOR LEVEL;

CRYPTOGRAPHY; HARDWARE; REENGINEERING; REVERSE ENGINEERING; SEMICONDUCTOR DEVICE MANUFACTURE;

EMBEDDED SYSTEMS;

EID: 70350599741     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-04138-9_26     Document Type: Conference Paper

References (6)

1. James, D.: A Case Study: Looking Inside Apple's iPOD Nano- a Teardown to the Atomic Scale, http://electronics.wesrch.com/Paper/paper details.php?id= EL1SE1KWRX174&paper type=pdf&type=author
2. Nii, H., et al.: A 45 nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA (1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL. In: IEDM 2006 Technical Digest, pp. 685-688 (2006)
3. Narasimha, S., et al.: High Performance 45 nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography. In: IEDM 2006 Technical Digest, pp. 689-692 (2006)
4. Chatterjee, A., et al.: A 65 nm CMOS Technology for Mobile and Digital Signal Processing Applications. In: IEDM 2004 Technical Digest, pp. 665-668 (2004)
5. 2005 ITRS, Metrology section
6. Vartanian, V., et al.: Metrology Challenges for 45 nm Strained-Si Devices. In: 2005 International Conference on Characterization and Metrology for ULSI Technology (2005)