Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator

Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013

Volumn , Issue , 2013, Pages 7-12

  Bichler, O ^a   Roclin, D ^a   Gamrat, C ^a   Querlioz, D ^b  

^a DIF   (France)

^b UNIVERSITÉ PARIS SACLAY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EVENT-DRIVEN SIMULATORS; FEATURES EXTRACTION; NEUROMORPHIC ARCHITECTURES; NEUROMORPHIC HARDWARES; PHASE CHANGE MEMORY (PCM); RESISTIVE RAMS (RRAM); SIMULATION STRATEGIES; SPIKE-TIMING-DEPENDENT PLASTICITY;

ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HARDWARE; MONTE CARLO METHODS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NEURAL NETWORKS; NEURONS; PHASE CHANGE MEMORY;

SIMULATORS;

EID: 84886773774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NanoArch.2013.6623029     Document Type: Conference Paper

References (32)

1. S. B. Furber, S. Temple, and A. D. Brown, "High-performance computing for systems of spiking neurons," University of Pennsylvania Law Review, vol. 154, no. 3, pp. 477+, 2006.
2. J. Schemmel, J. Fieres, and K. Meier, "Wafer-scale integration of analog neural networks," in Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on, 2008, pp. 431-438.
3. Choudhary, S. Sloan, S. Fok, A. Neckar, E. Trautmann, P. Gao, T. Stewart, C. Eliasmith, and K. Boahen, "Silicon neurons that compute," in International Conference on Artificial Neural Networks, vol. 7552, 2012, pp. 121-28.
4. J. Arthur, P. Merolla, F. Akopyan, R. Alvarez, A. Cassidy, S. Chandra, S. Esser, N. Imam, W. Risk, D. Rubin, R. Manohar, and D. Modha, "Building block of a programmable neuromorphic substrate: A digital neurosynaptic core," in Neural Networks (IJCNN), The 2012 International Joint Conference on, 2012, pp. 1-8.
5. G. Snider, "Spike-timing-dependent learning in memristive nanodevices," in Nanoscale Architectures, 2008. NANOARCH 2008. IEEE International Symposium on, 2008, pp. 85-92.
6. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale memristor device as synapse in neuromorphic systems," Nano Letters, vol. 10, no. 4, pp. 1297-1301, 2010.
7. S. Yu and H.-S. Wong, "Modeling the switching dynamics of programmable-metallization-cell (PMC) memory and its application as synapse device for a neuromorphic computation system," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 22.1.1- 22.1.4.
8. D. Querlioz, O. Bichler, and C. Gamrat, "Simulation of a memristorbased spiking neural network immune to device variations," in Neural Networks (IJCNN), The 2011 International Joint Conference on, 2011, pp. 1775-1781.
9. C. Zamarreno-Ramos, L. A. Camunas-Mesa, J. A. Perez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, and B. Linares-Barranco, "On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex," Frontiers in Neuroscience, vol. 5, no. 26, 2011.
10. G. Indiveri, B. Linares-Barranco, T. J. Hamilton, A. van Schaik, R. Etienne-Cummings, T. Delbruck, S.-C. Liu, P. Dudek, P. Hafliger, S. Renaud, J. Schemmel, G. Cauwenberghs, J. Arthur, K. Hynna, F. Folowosele, S. Saighi, T. Serrano-Gotarredona, J. Wijekoon, Y. Wang, and K. Boahen, "Neuromorphic silicon neuron circuits," Frontiers in Neuroscience, vol. 5, no. 73, 2011.
11. VHDL Language Reference Manual, IEEE Std. 1076-2008, 2009.
12. SystemC Language Reference Manual, IEEE Std. 1666-2005, 2006.
13. N. Carnevale and M. Hines, The NEURON Book. New York, NY, USA: Cambridge University Press, 2006.
14. D. Goodman and R. Brette, "Brian: a simulator for spiking neural networks in python," Frontiers in Neuroinformatics, vol. 2, no. 5, 2008.
15. M.-O. Gewaltig and M. Diesmann, "NEST (NEural Simulation Tool)," Scholarpedia, vol. 2, no. 4, p. 1430, 2007.
16. F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, no. 7, p. 075201, 2012.
17. M. Suri, O. Bichler, D. Querlioz, G. Palma, E. Vianello, D. Vuillaume, C. Gamrat, and B. DeSalvo, "CBRAM devices as binary synapses for low-power stochastic neuromorphic systems: Auditory (cochlea) and visual (retina) cognitive processing applications," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, in press.
18. C++11, ISO/IEC Std. 14 882:2011, 2011.
19. A. Delorme, J. Gautrais, R. van Rullen, and S. Thorpe, "SpikeNET: A simulator for modeling large networks of integrate and fire neurons," Neurocomputing, vol. 26, pp. 989-996, 1999.
20. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128×128 120 dB 15 ?s latency asynchronous temporal contrast vision sensor," Solid-State Circuits, IEEE Journal of, vol. 43, no. 2, pp. 566-576, 2008.
21. S.-C. Liu, A. van Schaik, B. Minch, and T. Delbruck, "Event-based 64- channel binaural silicon cochlea with Q enhancement mechanisms," in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 2027-2030.
22. D. Querlioz, O. Bichler, P. Dollfus, and C. Gamrat, "Immunity to device variations in a spiking neural network with memristive nanodevices," Nanotechnology, IEEE Transactions on, 2013, in press.
23. T. Delbruck, B. Linares-Barranco, E. Culurciello, and C. Posch, "Activity-driven, event-based vision sensors," in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 2426-2429.
24. D. Querlioz, P. Dollfus, O. Bichler, and C. Gamrat, "Learning with memristive devices: How should we model their behavior?" in Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on, 2011, pp. 150 -156.
25. O. Bichler, D. Querlioz, S. Thorpe, J. Bourgoin, and C. Gamrat, "Unsupervised features extraction from asynchronous silicon retina through spike-timing-dependent plasticity," in Neural Networks (IJCNN), The 2011 International Joint Conference on, 2011, pp. 859-866.
26. M. Suri, O. Bichler, D. Querlioz, O. Cueto, L. Perniola, V. Sousa, D. Vuillaume, C. Gamrat, and B. DeSalvo, "Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011.
27. O. Bichler, M. Suri, D. Querlioz, D. Vuillaume, B. DeSalvo, and C. Gamrat, "Visual pattern extraction using energy-efficient '2-PCM synapse' neuromorphic architecture," Electron Devices, IEEE Transactions on, vol. 59, no. 8, pp. 2206-2214, 2012.
28. D. Kuzum, R. Jeyasingh, S. Yu, and H.-S. Wong, "Low-energy robust neuromorphic computation using synaptic devices," Electron Devices, IEEE Transactions on, vol. 59, no. 12, pp. 3489-3494, 2012.
29. V. Simonis and R. Weiss, "Heterogeneous, nested STL containers in C++," in Perspectives of System Informatics, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2000, vol. 1755, pp. 383-388.
30. M. Matsumoto and T. Nishimura, "Mersenne twister: a 623- dimensionally equidistributed uniform pseudo-random number generator," ACM Trans. Model. Comput. Simul., vol. 8, no. 1, pp. 3-30, 1998.
31. D. Querlioz, O. Bichler, M. Suri, J. Larroque, Z. W.S., J.-O. Klein, S. Retailleau, P. Dollfus, B. De Salvo, and C. Gamrat, "Simulation of a bio-inspired system capable of learning thanks to stochastic nanodevices," Applied Physics Letters, 2013, (submitted).
32. D. Roclin, O. Bichler, C. Gamrat, S. J. Thorpe, and J.-O. Klein, "Design study of an efficient digital order-based STDP neuron implementation for temporal features extraction," in Neural Networks (IJCNN), The 2013 International Joint Conference on, 2013, (accepted).