Core network interface architecture and latency constrained on-chip communication

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 358-363

  Bhojwani, Praveen ^a   Mahapatra, Rabi N ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE VALIDATION; END-TO-END LATENCY; LATENCY VARIATIONS; ON CHIP COMMUNICATION; ON-CHIP INTERCONNECTION NETWORK; ON-CHIP NETWORKS; SYSTEMS-ON-A-CHIP; VIRTUAL CHANNELS;

COMMUNICATION; EMBEDDED SYSTEMS; JITTER; PACKET NETWORKS; ROUTERS;

MICROPROCESSOR CHIPS;

EID: 84886743030     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.41     Document Type: Conference Paper

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