A heuristic for peak power constrained design of Network-on-Chip (NoC) based multimode systems

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 124-129

  Bhojwani, Praveen ^a   Mahapatra, Rabi ^a   Kim, Eun Jung ^a   Chen, Thomas ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK-ON-CHIP (NOC); POWER CONSUMPTION; SYSTEM COMPONENTS; SYSTEM PERFORMANCE;

COMPUTER SIMULATION; ELECTRIC POWER SYSTEM INTERCONNECTION; FREQUENCY ALLOCATION; ROUTERS;

MICROPROCESSOR CHIPS;

EID: 27944447933     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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