Efficient and accurate modeling of power supply noise on distributed on-chip power networks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2000, Pages

  Zheng, L R ^a   Li, B X ^a   Tenhunen, H ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INDUCTANCE MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL;

ON-CHIP DECOUPLING EFFECTS; ON-CHIP POWER NETWORKS; SOFTWARE PACKAGE SPICE;

POWER ELECTRONICS;

EID: 0033714236     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856378     Document Type: Conference Paper

References (6)