Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2000, Pages 65-72

  Zhao, Shiyou ^a   Roy, Kaushik ^a   Koh, Cheng Kok ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; GENETIC ALGORITHMS; INDUCTANCE MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MONTE CARLO METHODS; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE; VECTORS; WAVEFORM ANALYSIS;

DEEP SUB-MICRON CIRCUITS; INDUCTIVE-RESISTIVE SWITCHING NOISES;

CMOS INTEGRATED CIRCUITS;

EID: 0033712726     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)