Detecting malicious landing pages in malware distribution networks

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2013, Pages

  Wang, Gang ^a   Stokes, Jack W ^b   Herley, Cormac ^b   Felstead, David ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Drive by download; malware distribution network; signature

Indexed keywords

DRIVE-BY DOWNLOAD; LANDING PAGES; MALWARES; SIGNATURE;

LANDING;

COMPUTER CRIME;

EID: 84883376655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2013.6575316     Document Type: Conference Paper

References (26)

1. T. Siddiqua and S. Gurumurthi Recovery boosting: A technique to enhance NBTI recovery in SRAM arrays, Proceedings of the IEEE Annual Symposium on VLSI, pp. 393-398, 2010.
2. K. Kang, S. Gangwal, S. Park, and K. Roy NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? Design Automation Conference, Asia and South Pacific, pp. 726-731, March 2008.
3. R. Vattikonda, W. Wang, and Y. Cao Modeling and minimization of PMOS NBTI effect for robust nanometer design, Proceedings of the 43rd annual Design Automation Conference DAC, pp. 1047-1052, 2006.
4. A. Bansal, R. M. Rao, J.-J. Kim, S. Zafar, J. H. Stathis, and C.-T. Chuang Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability, Microelectronics Reliability, pp. 642-649, 2009.
5. G. Memik, M. Kandemir, and O. Ozturk Increasing register file immunity to transient errors, Design, Automation and Test in Europe, Proceedings, pp. 586-591, March 2005.
6. J. A. Blome, S. Gupta, S. Feng, and S. Mahlke Cost-efficient soft error protection for embedded microprocessors, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pp. 421-431, 2006.
7. H. Amrouch and J. Henkel Self-immunity technique to improve register file integrity against soft errors, VLSI Design, 24th International Conference on, pp. 189-194, Jan. 2011.
8. B. Calhoun and A. Chandrakasan Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS, Solid-State Circuits Conference. Proceedings of the 31st European, pp. 363-366, Sept. 2005.
9. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula Predictive modeling of the NBTI effect for reliable design, Custom Integrated Circuits Conference, CICC '06. IEEE, pp. 189-192, 2006.
10. W. Zhao and Y. Cao Predictive technology model for nano-CMOS design exploration, J. Emerg. Technol. Comput. Syst., April 2007.
11. K. Arabi, R. Saleh, and M. Xiongfei Power supply noise in SoCs: Metrics, management, and measurement, Design Test of Computers, IEEE, vol. 24, no. 3, pp. 236-244, May-June 2007.
12. A. Pavlov and M. Sachdev, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test, 1st ed. Springer Publishing Company, Incorporated, 2008.
13. F. Mesa, M. Brown, J. Nayfach, and J. Renau Measuring power and temperature from real processors, Parallel and Distributed Processing, IEEE International Symposium on, pp. 1-5, April 2008.
14. I. K. Yongkui Han and C. Mritz Temperature aware floorplanning, Temperature-Aware Computer Systems, June 2005.
15. K. Kang, H. Kufluoglu, K. Roy, and M. Ashraful Alam Impact of negative-bias temperature instability in nanoscale SRAM array: Modeling and analysis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, pp. 1770-1781, Oct. 2007.
16. J. Abella, X. Vera, and A. Gonzalez Penelope: The NBTI-aware processor, Microarchitecture. 40th Annual IEEE/ACM International Symposium on, pp. 85-96, Dec. 2007.
17. L. Li, Y. Zhang, J. Yang, and J. Zhao Proactive NBTI mitigation for busy functional units in out-of-order microprocessors, Proceedings of the Conference on Design, Automation and Test, pp. 411-416, 2010.
18. S. Kothawade, K. Chakraborty, and S. Roy Analysis and mitigation of NBTI aging in register file: An end-to-end approach, Quality Electronic Design, 12th International Symposium on, pp. 1-7, March 2011.
19. Y. Kunitake, T. Sato, and H. Yasuura Signal probability control for relieving NBTI in SRAM cells, Quality Electronic Design (ISQED), 11th International Symposium on, pp. 660-666, March 2010.
20. S. Wang, T. Jin, C. Zheng, and G. Duan Low power aging-aware register file design by duty cycle balancing, Design, Automation Test in Europe Conference Exhibition (DATE), pp. 546-549, March 2012.
21. J. Tandon The openrisc processor: open hardware and linux, Linux J., Dec. 2011.
22. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown Mibench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, IEEE International Workshop, pp. 3-14, 2001.
23. C. Lee, M. Potkonjak, and W. H. Mangione-Smith Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, pp. 330-335, 1997.
24. Faraday Memory Compiler Architecture, http://www.faradaytech.com/index. html.
25. R. Preston, R. Badeau, D. Bailey, S. Bell, L. Biro, W. Bowhill, D. Dever, S. Felix, R. Gammack, V. Germini, M. Gowan, P. Gronowski, D. Jackson, S. Mehta, S. Morton, J. Pickholtz, M. Reilly, and M. Smith Design of an 8-wide superscalar risc microprocessor with simultaneous multithreading, Solid-State Circuits Conference, Digest of Technical Papers. IEEE International, pp. 334-472, Feb. 2002.
26. R. Azevedo, S. Rigo, M. Bartholomeu, G. Araujo, C. Araujo, and E. Barros The ArchC architecture description language and tools, International Journal of Parallel Programming, pp. 453-484, 2005