Minimal-path fault-tolerant approach using connection-retaining structure in networks-on-chip

2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013

Volumn , Issue , 2013, Pages

  Ebrahimi, Masoumeh ^a   Daneshtalab, Masoud ^a   Plosila, Juha ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT-TOLERANT; FAULT-TOLERANT METHOD; FAULT-TOLERANT ROUTING ALGORITHM; NETWORKS ON CHIPS; NEW FORMS; ON-CHIP NETWORKS; ROUTER ARCHITECTURE; SHORTEST PATH;

ALGORITHMS; COMPUTER ARCHITECTURE; GRAPH THEORY; ROUTERS; ROUTING ALGORITHMS;

NETWORK ARCHITECTURE;

EID: 84881436882     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NoCS.2013.6558401     Document Type: Conference Paper

References (22)

1. Xu, Jiang, W. Wolf, J. Hankel, S. Charkdhar, "A Methodology for design, modeling and analysis for networks-on-Chip," in Proc. of IEEE International Symposium on Circuits and Systems, pp. 1778-1781, 2005.
2. W. Tsai, D. Zheng, S. Chen, and Y.H. Hu, "A fault-tolerant NoC scheme using bidirectional channel", in Proc. DAC, pp.918-923, 2011.
3. E. Rijpkema et al., "Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip," in Proc. of DATE'03, pp. 350-355, 2003.
4. M. Ali, M. Welzl, S.Hessler, "A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip," in Proc. of international conference on Information Technology, pp.1027-1032, 2007.
5. J. Duato, S. Yalamanchili, L. Ni, "Interconnection networks: An engineering approach", Morgan Kaufmann Publishers, 2003.
6. M. Daneshtalab, M. Kamali, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, and J. Plosila, "Adaptive Input-output Selection Based On-Chip Router Architecture," Journal of Low Power Electronics (JOLPE), Vol. No. 1, pp. 11-29, 2012.
7. J. Wu, "A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model", IEEE transaction on computers, v. 52, pp.1154-1169, 2003.
8. F. Chaix, et al., "A fault-tolerant deadlock-free adaptive routing for On Chip interconnects," in Proc. of DATE, pp. 1-4, 2011.
9. S. Jovanovic, C. Tanougast, et al., "A new deadlock-free fault-tolerant routing algorithm for NoC interconnections", in Proc. of FPL, pp.326-331, 2009.
10. J. Wu and D. Wang, "Fault-tolerant and deadlock-free routing in 2-D meshes using rectilinear-monotone polygonal fault blocks", in Proc. of Parallel Algorithms., pp.99-111, 2005.
11. Z. Zhen, A. Greiner, S. Taktak, "A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip", DAC, pp. 441-446, 2008.
12. M. Ebrahimi et al., "MD: Minimal path-based Fault-Tolerant Routing in On-Chip Networks," in Proc. of ASP-DAC, pp. 35-40, 2013.
13. M. Ebrahimi et al., "MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip," in Proc. of DSD, pp. 201-206, 2012.
14. M. Ebrahimi et al., "High Performance Fault-Tolerant Routing Algorithm for NoC-based Many-Core Systems," in Proc. of PDP, 2013.
15. D. Fick. A. DeOrio, G. Chen, v. Bertacco, D. Sylverster, D.Blaauw, "A highly resilient routing algorithm for fault-tolerant NoCs", in Proc. of DATE, pp. 21-26, 2009.
16. Ch. Feng, Zh. L, A. Jantsch, J. Li, M. Zhang, "A Reconfigurable Faulttolerant Deflection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip", in Proc. of NoCArc, 2010.
17. M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks in Proc of NOCS, pp. 19-26, 2012.
18. F. Chaix, D. Avresky, N. Zergainoh, M. Nicolaidis, "Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems", in Proc. of NCA, pp.52-59, 2010.
19. W. Tsai, D. Zheng, S. Chen, and Y.H. Hu, "A fault-tolerant NoC scheme using bidirectional channel", in Proc. of DAC, pp.918-923, 2011.
20. M. Valinataja, S. Mohammadi, J. Plosila, P. Liljeberg, H. Tenhunen, "A reconfigurable and adaptive routing method for fault-tolerant meshbased networks-on-chip," International Journal of Electronics and Communications (AEU), v. 65, I.7, pp. 630-640, 2011.
21. M. Koibuchi, H. Matsutani, H. Amano, T.M. Pinkston, "A Lightweight Fault-Tolerant Mechanism for Network-on-Chip", in Proc. of NoCS -22, 2008.
22. C.J. Glass et al., "The Turn Model for Adaptive Routing", in Proc. of 19th Int'l Symp. Computer Architecture, pp. 278-287, 1992.