Adaptive Input-Output Selection based on-chip router architecture

Journal of Low Power Electronics

Volumn 8, Issue 1, 2012, Pages 11-29

  Daneshtalab, M ^a,b   Kamali, M ^c   Ebrahimi, M ^a   Mohammadi, S ^b   Afzali Kusha, A ^b   Plosila, J ^a  

^a UNIVERSITY OF TURKU   (Finland)

^b UNIVERSITY OF TEHRAN   (Iran)

^c ÅBO AKADEMI UNIVERSITY   (Finland)

Author keywords

Arbitration mechanism; Networks on chip; Power consumption; Routing algorithm

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; GENETIC ALGORITHMS; NETWORK ROUTING; NETWORK-ON-CHIP; ROUTING ALGORITHMS;

ARBITRATION MECHANISMS; BASE-LINE ARCHITECTURE; CONGESTION CONDITIONS; INPUT-OUTPUT SELECTION; MULTICAST COMMUNICATION; NETWORK CONGESTIONS; NETWORKS ON CHIPS; ROUTER ARCHITECTURE;

NETWORK ARCHITECTURE;

EID: 84861505380     PISSN: 15461998     EISSN: 15462005     Source Type: Journal    
DOI: 10.1166/jolpe.2012.1165     Document Type: Conference Paper

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