3D power delivery for microprocessors and high-performance ASICs

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn , Issue , 2007, Pages 127-133

  Sun, Jian ^a   Lu, Jian Qiang ^a   Giuliano, David ^a   Chow, T Paul ^a   Gutmann, Ronald J ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DYNAMIC RESPONSE; ELECTRIC POWER TRANSMISSION; EXHIBITIONS; INTEGRATION; STANDARDS; THREE DIMENSIONAL;

(+ MOD 2N) OPERATION; 3D DESIGN; APPLIED (CO); BASIC BUILDING BLOCKS; BUCK CONVERTERS; CELLULAR ARCHITECTURE; CHIP AREAS; CONTROL BANDWIDTH; CONVENTIONAL POWER; CONVERTER CELLS; DESIGN TRADE-OFFS; DYNAMIC REGULATION; FUNDAMENTAL LIMITATIONS; IC TECHNOLOGIES; IMPLEMENTATION METHODS; INPUT AND OUTPUT (I/O); INTERCONNECT PARASITICS; LOSS BREAKDOWN; PARALLEL OPERATIONS; POWER DELIVERY; POWER REQUIREMENTS; POWER SUPPLIES; RATED OUTPUT; SCALING-UP; STEP CHANGES; THREE DIMENSIONAL (3-D) INTEGRATION; THREE DIMENSIONAL (3D);

POWER ELECTRONICS;

EID: 34748909644     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEX.2007.357505     Document Type: Conference Paper

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