ECM: Effective Capacity Maximizer for high-performance compressed caching

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 131-142

  Baek, Seungcheol ^a   Lee, Hyung Gyu ^b   Nicopoulos, Chrysostomos ^c   Lee, Junghee ^a   Kim, Jongman ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Daegu University   (South Korea)

^c UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISS REDUCTION; EFFECTIVE CAPACITY; EXTENSIVE SIMULATIONS; FULL SYSTEM SIMULATORS; FUNDAMENTAL PRINCIPLES; INTERVAL PREDICTION; LASTLEVEL CACHES (LLC); PERFORMANCE IMPROVEMENTS;

COMPRESSION RATIO (MACHINERY); SUPERCOMPUTERS;

COMPUTER ARCHITECTURE;

EID: 84880288504     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522313     Document Type: Conference Paper

References (21)

1. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2010.
2. A.-R. Adl-Tabatabai, A. M. Ghuloum, and S. O. Kanaujia. Compression in cache design. In Proceedings of the 21st an-nual international conference on Supercomputing, ICS '07, pages 190-201, New York, NY, USA, 2007. ACM.
3. A. R. Alameldeen and D. A.Wood. Adaptive cache compression for high-performance processors. In Proceedings of the 31st annual international symposium on Computer architec-ture, ISCA '04, pages 212-, Washington, DC, USA, 2004. IEEE Computer Society.
4. A. R. Alameldeen and D. A. Wood. Frequent pattern compression: A significance-based compression scheme for l2 caches. In Technical Report 1500, University of Wisconsin-Madison, 2004. Computer Sciences Department.
5. R. Bagrodia and et al. Parsec: A parallel simulation environment for complex systems. Computer, 31:77-85, October 1998.
6. X. Chen, L. Yang, R. Dick, L. Shang, and H. Lekatsas. Cpack: A high-performance microprocessor cache compression algorithm. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 18(8):1196-1208, aug. 2010.
7. P. Franaszek, J. Robinson, and J. Thomas. Parallel compression with cooperative dictionary construction. In Proceedings of the Conference on Data Compression, DCC '96, pages 200-, Washington, DC, USA, 1996. IEEE Computer Society.
8. E. Hallnor and S. Reinhardt. A unified compressed memory hierarchy. In High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on, pages 201-212, feb. 2005.
9. E. G. Hallnor and S. K. Reinhardt. A compressed memory hierarchy using an indirect index cache. In Proceedings of the 3rd workshop on Memory performance issues: in con-junction with the 31st international symposium on computer architecture, WMPI '04, pages 9-15, New York, NY, USA, 2004. ACM.
10. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer. Adaptive insertion policies for managing shared caches. In Proceedings of the 17th international conference on Parallel architectures and compilation tech-niques, PACT '08, pages 208-219, New York, NY, USA, 2008. ACM.
11. A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (rrip). In Proceedings of the 37th annual in-ternational symposium on Computer architecture, ISCA '10, pages 60-71, New York, NY, USA, 2010. ACM.
12. S. Kim, J. Lee, J. Kim, and S. Hong. Residue cache: A lowenergy low-area l2 cache architecture via compression and partial hits. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, pages 420-429, New York, NY, USA, 2011. ACM.
13. J.-S. Lee, W.-K. Hong, and S.-D. Kim. An on-chip cache compression technique to reduce decompression overhead and design complexity. J. Syst. Archit., 46(15):1365-1382, Dec. 2000.
14. H. Liu, M. Ferdman, J. Huh, and D. Burger. Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency. In Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, MICRO 41, pages 222-233, Washington, DC, USA, 2008. IEEE Computer Society.
15. P. S. Magnusson and et al. Simics: A full system simulation platform. Computer, 35:50-58, February 2002.
16. M.M. K.Martin, D. J. Sorin, B.M. Beckmann, M. R.Marty, M. Xu, A. R. Alameldeen, K. E.Moore, M. D. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Computer Architecture News, 33:2005, 2005.
17. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely, and J. Emer. Adaptive insertion policies for high performance caching. In Proceedings of the 34th annual international symposium on Computer architecture, ISCA '07, pages 381-391, New York, NY, USA, 2007. ACM.
18. L. Villa, M. Zhang, and K. Asanovic. Dynamic zero compression for cache energy reduction. In Proceedings of the 33rd annual ACM/IEEE international symposium on Mi-croarchitecture, MICRO 33, pages 214-220, New York, NY, USA, 2000. ACM.
19. C.-J. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. C. Steely, Jr., and J. Emer. Ship: signature-based hit predictor for high performance caching. In Proceedings of the 44th An-nual IEEE/ACM International Symposium on Microarchitec-ture, MICRO-44 '11, pages 430-441, New York, NY, USA, 2011. ACM.
20. Y. Xie and G. Loh. Thread-aware dynamic shared cache compression in multi-core processors. In Computer Design (ICCD), 2011 IEEE 29th International Conference on, pages 135-141, oct. 2011.
21. J. Yang, Y. Zhang, and R. Gupta. Frequent value compression in data caches. In Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, MICRO 33, pages 258-265, New York, NY, USA, 2000. ACM.