Modeling power consumption of NAND flash memories using flashpower

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 7, 2013, Pages 1031-1044

  Mohan, Vidyabhushan ^a   Bunker, Trevor ^b   Grupp, Laura ^b   Gurumurthi, Sudhanva ^a   Stan, Mircea R ^a   Swanson, Steven ^b  

^a University of Virginia   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analytical models; NAND Flash memory; power

Indexed keywords

ARCHITECTURE COMMUNITY; CONSUMER ELECTRONICS PRODUCTS; DESIGN SPACE EXPLORATION; MEMORY ORGANIZATIONS; MULTI LEVEL CELL (MLC); NAND FLASH MEMORY; POWER; POWER CHARACTERISTIC;

ANALYTICAL MODELS; CONSUMER ELECTRONICS; MEMORY ARCHITECTURE; NAND CIRCUITS; TOOLS; VIRTUAL STORAGE;

FLASH MEMORY;

EID: 84879927002     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2013.2249557     Document Type: Article

References (30)

1. C. Dirik and B. Jacob, "The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization," in Proc. Int. Symp. Computer Architecture (ISCA), 2009, pp. 279-289.
2. N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, "Design tradeoffs for SSD performance," in Proc. USENIX Tech. Conf. (USENIX), 2008, pp. 57-70.
3. T. Kgil, D. Roberts, and T. Mudge, "Improving NAND Flash based disk caches," in Proc. Int. Symp. Computer Architecture, 2008, pp. 327-338.
4. A. M. Caulfield, L. M. Grupp, and S. Swanson, "Gordon: Using Flash memory to build fast, power-efficient clusters for data-intensive applications," in Proc. Int. Conf. Architectural Support Programming Languages Operating Systems (ASPLOS), 2009, pp. 217-228.
5. J. K. Kim, H. G. Lee, S. Choi, and K. Il Bahng, "A PRAM andNANDFlash hybrid architecture for high-performance embedded storage subsystems," in Proc. 8th ACM Int. Conf. Embedded Software, 2008, pp. 31-40.
6. E. Gal and S. Toledo, "Algorithms and data structures for Flash memories," ACM Comput. Surveys, vol. 37, no. 2, pp. 138-163, 2005. (Pubitemid 41527575)
7. A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A Flash translation layer employing demand-based selective caching of page-level address mappings," in Proc. 14th Int. Conf. Architectural Support Programming Languages Operating Syst., 2009, pp. 229-240.
8. C. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. Stan, "Relaxing non-volatility for fast and energy-efficient STT-RAM caches," in Proc. IEEE 17th Int. Symp. HPCA, Feb. 2011, pp. 50-61.
9. S.Wilton and N. Jouppi, "Cacti: An enhanced cache access and cycle time model," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 677-688, May 1996.
10. J. Brewer and M. Gill, Eds., Nonvolatile Memory Technologies With Emphasis on Flash. New York, USA: IEEE Press, 2008.
11. K.-D. Suh, B.-H. Suh, Y.-H. Um, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, and J.-R. Kim, H.-K. Lim, "A 3.3V 32 Mb NAND Flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
12. T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K. Ohuchi, F. Masuoka, and H. Hara, "A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-onlyNANDFlash memory," IEEE J. Solid-State Circuits, vol. 29, no. 11, pp. 1366-1373, Nov. 1994.
13. K. Takeuchi, T. Tanaka, and T. Tanzawa, "A multipage cell architecture for high-speed programming multilevel NAND Flash memories," IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1228-1238, Aug. 1998.
14. Process Integration and Device Structures, ITRS 2011 Edition [Online]. Available: http://www.itrs.net/Links/2011ITRS/2011Tables/PIDS2011Tables.xlsx
15. J. Lee, S.-S. Lee, O.-S. Kwon, K.-H. Lee, D.-S. Byeon, I.-Y. Kim, K.- H. Lee, Y.-H. Lim and B.-S. Choi and J.-S. Lee, W.-C. Shin, J.-H. Choi, and K.-D. Suh, "A 90-nm CMOS 1.8-V 2-Gb NAND Flash memory for mass storage applications," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1934-1942, Nov. 2003.
16. D. T.Wang, "ModernDRAMmemory systems: Performance analysis and a high performance, power-constrainedDRAMscheduling algorithm," Ph.D. dissertation, Univ. Maryland, College Park, MD, USA, 2005.
17. M. Lenzlinger and E. Snow, "Fowler-Nordheim tunneling into thermally grown SiO2," IEEE Trans. Electron Devices, vol. 15, no. 9, pp. 686-686, Sep. 1968.
18. Samsung Corporation, "K9XXG08XXM Flash memory specification," K9XXG08XXM Datasheet.
19. K. Sakui, Intel Corporation/Tohoku University, May 2009, private correspondence.
20. K. Ishida, K. Yasufuku, T. Miyamoto, S. Nakai, H. Takamiya, M. Sakurai, T. Takeuchi, "A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND Flash SSD," in Proc. Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 238-239, 239a.
21. T. Bunker, M. Wei, and S. Swanson, "Ming II: A Flexible platform for NAND Flash-based research," Dept. Comput. Sci. Eng., Univ. California, San Diego, CA, USA, Tech. Rep. CS2012-0978, 2012.
22. L.M. Grupp, A.M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P.H. Siegel, J.K.Wolf, "Characterizing Flash memory: Anomalies, observations, and applications," in Proc. 42nd IEEE/ACM MICRO, 2009, pp. 24-33.
23. H. Schmidt, D.Walter, F. Gliem, B. Nickson, R. H.-Sorensen, A. Virtanen, "Tid and see tests of an advanced 8 gbit NAND-FLASH memory," in Proc. IEEE Radiation Effects Data Workshop, Jul. 2008, pp. 38-41.
24. C. W. Smullen, IV, A. Nigam, S. Gurumurthi, and M. R. Stan, "The STeTSiMS STT-RAM simulation and modeling system," in Proc. Int. Conf. Comput.-Aided Design, 2011, pp. 318-325.
25. X. Dong, N. P. Jouppi, and Y. Xie, "PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM," in Proc. Int. Conf. Comput.-Aided Des., 2009, pp. 269-275.
26. C. Xu, X. Dong, N. Jouppi, and Y. Xie, "Design implications of memristor-based RRAM cross-point structures," in Proc. DATE, 2011, pp. 1-6.
27. E. Yaakobi, J. Ma, L. Grupp, P. Siegel, S. Swanson, and J. Wolf, "Error characterization and coding schemes for flash memories," in Proc. IEEE GLOBECOM Workshops, Dec. 2010, pp. 1856-1860.
28. S. Boboila and P. Desnoyers, "Write endurance in Flash drives: Measurements and analysis," in Proc. USENIX Conf. File and Storage Technol., 2010.
29. NVSim [Online]. Available: http://www.rioshering.com/nvsimwiki/index.php? title=MainPage
30. M. Jung, E. Wilson, D. Donofrio, J. Shalf, and M. Kandemir, "NANDFlashSim: Intrinsic latency variation aware NAND Flash memory system modeling and simulation at microarchitecture level," in Proc. IEEE 28th Symp. Mass Storage Syst. Technol., Apr. 2012, pp. 1-12.