Error characterization and coding schemes for flash memories

2010 IEEE Globecom Workshops, GC'10

Volumn , Issue , 2010, Pages 1856-1860

  Yaakobi, Eitan ^a   May, Jing ^b   Grupp, Laura ^a   Siegel, Paul H ^a   Swanson, Steven ^a   Wolf, Jack K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ERRORS;

BCH CODE; BIT LEVEL; CODING SCHEME; ERASE OPERATION; ERROR CHARACTERIZATIONS; ERROR CORRECTING SCHEME; ERROR-CODING; READ OPERATION; WRITE OPERATIONS;

FLASH MEMORY;

EID: 79951934944     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOMW.2010.5700263     Document Type: Conference Paper

References (6)

1. Y. Cassuto, M. Schwartz, V. Bohossian, and J. Bruck, "Codes for asymmetric limited-magnitude errors with applications to multilevel flash memories," IEEE Trans. on Inform. Theory, vol. 56, no. 4, pp. 1582-1595, April 2010.
2. E. Gal and S. Toledo, "Algorithms and data structures for flash memories," ACM Computing Surveys, vol. 37, pp. 138-163, June 2005.
3. S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, "On-chip error correcting techniques for new-generation flash memories," Proceedings of The IEEE, vol. 91, no. 4, pp. 602-616, April 2003.
4. L. Grupp, A. Caulfield, J. Coburn, S. Swanson, E.Yaakobi, P.H. Siegel, and J.K.Wolf, "Characterizing flash memory : anomalies, observations, and applications," MICRO-42, pp. 24-33, December 2009.
5. N. Mielke, T. Marquart, N.Wu, J.Kessenich, H. Belgal, E. Schares, F. Triverdi, "Bit error rate in NAND flash memories,"in Proceedings of IEEE Reliability Physics Symposium, pp. 9-19, May 2008.
6. R.L. Rivest and A. Shamir, "How to reuse a write-once memory," Information and Control, vol. 55, no. 1-3, pp. 1-19, December 1982.