DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings

ACM SIGPLAN Notices

Volumn 44, Issue 3, 2009, Pages 229-240

  Gupta, Aayush ^a   Kim, Youngjae ^a   Urgaonkar, Bhuvan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Flash Management; Flash Translation Layer; Storage System

Indexed keywords

EXPERIMENTAL EVALUATION; FINANCIAL INSTITUTION; FLASH DEVICES; FLASH MANAGEMENT; FLASH TECHNOLOGY; FLASH TRANSLATION LAYER; GARBAGE COLLECTION; GARBAGE COLLECTORS; HARD DISKS; I/O TRACES; MECHANICAL MOVING PARTS; PARADIGM SHIFTS; POOR PERFORMANCE; RESPONSE TIME; SIMULATION FRAMEWORK; STORAGE MEDIA; STORAGE SYSTEM; STORAGE SYSTEMS; SYSTEM RESPONSE TIME; TECHNOLOGICAL ADVANCES; VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATIONS; WORKLOAD CHARACTERISTICS;

EMBEDDED SYSTEMS; REFUSE COLLECTION; RESPONSE TIME (COMPUTER SYSTEMS); WASTE DISPOSAL;

FLASH MEMORY;

EID: 67650783129     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (28)

1. Amir Ban. Flash File System. In United States Patent, No 5,404,485, 1993.
2. T. Chung, D. Park, S. Park, D. Lee, S. Lee, and H. Song. System Software for Flash Memory: A Survey. In Proceedings of the International Conference on Embedded and Ubiquitous Computing, pages 394-404, August 2006.
3. E. Gal and S. Toledo. Algorithms and Data Structures for Flash Memories. ACM Computing Survey, 37(2):138-163, 2005. ISSN 0360-0300.
4. Flash Drives Hit by High Failure Rates. Flash Drives Hit by High Failure Rates. http://www.techworld.com/ storage/news/index.cfm?newsid=11747.
5. G.R. Ganger, B.L. Worthington, and Y.N. Patt. The DiskSim Simulation Environment Version 3.0 Reference Manual.
6. A. Gulati, A. Merchant, and P. J. Varman. pClock: An Arrival Curve based Approach for QoS Guarantees in Shared Storage Systems. In Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pages 13-24, June 2007.
7. A. Gupta, Y. Kim, and B. Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. In Technical Report CSE 08-012, Penn State University, August 2008.
8. S. Gurumurthi, A. Sivasubramaniam, M. Kandemir, and H. Franke. DRPM: Dynamic Speed Control for Power Management in Server Class Disks. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 169-179, June 2003.
9. J. Hennessy and D. Patterson. Computer Architecture - A Quantitative Approach. Morgan Kaufmann, 2003.
10. HP Labs. Tools and Traces. HP Labs. Tools and Traces. http://tesla.hpl.hp.com/public-software/.
11. J. Kim, J.M. Kim, S.H. Noh, S. Min, and Y. Cho. A Space-Efficient Flash Translation Layer for Compactflash Systems. IEEE Transactions on Consumer Electronics, 48(2):366-375, 2002.
12. D. Jung, Y. Chae, H. Jo, J. Kim, and J. Lee. A Group-based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pages 160-164, September 2007. ISBN 978-1-59593-826-8.
13. J. Kang, H. Jo, J. Kim, and J. Lee. A Superblock-based Flash Translation Layer for NAND Flash Memory. In Proceedings of the International Conference on Embedded Software (EM-SOFT), pages 161-170, October 2006. ISBN 1-59593-542-8.
14. R. Karedla, J. Spencer Love, and Bradley G. Wherry. Caching Strategies to Improve Disk System Performance. IEEE Transactions on Computer, 27(3):38-46, 1994. ISSN 0018-9162.
15. A. Kawaguchi, S. Nishioka, and H. Motoda. A Flash-Memory based File System. In Proceedings of the Winter 1995 USENIX Technical Conference, pages 155-164, 1995.
16. H. Kim and S. Ahn. BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In Proceedings of the USENIX Conference on File and Storage Technologies (FAST), pages 1-14, Feburary 2008.
17. Y. Kim, S. Gurumurthi, and A. Sivasubramaniam. Understanding the Performance-Temperature Interactions in Disk I/O of Server Workloads. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), Febuary 2006.
18. S. Lee and B. Moon. Design of Flash-based DBMS: An In-Page Logging Approach. In Proceedings of the International Conference on Management of Data (SIGMOD), pages 55-66, August 2007. ISBN 978-1-59593-686-8.
19. S. Lee, D. Park, T. Chung, D. Lee, S. Park, and H. Song. A Log Buffer based Flash Translation Layer Using Fully Associative Sector Translation. IEEE Transactions on Embedded Computing Systems, 6(3):18, 2007. ISSN 1539-9087.
20. S. Lee, D. Shin, Y. Kim, and J. Kim. LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems. In Proceedings of the International Workshop on Storage and I/O Virtualization, Performance, Energy, Evaluation and Dependability (SPEED2008), Feburary 2008.
21. A. Leventhal. Flash Storage Memory. Communications of the ACM, 51(7):47-51, 2008. ISSN 0001-0782.
22. K. M. J. Lofgren, R. D. Norman, G B. Thelin, and A. Gupta. Wear Leveling Techniques for Flash EEPROM. In United States Patent, No 6,850,443, 2005.
23. Micron 16GB Mass Storage. Micron 16GB Mass Storage. http://www.micron. com/products/ partdetail?part=MT29F16G08DAAWP.
24. Micron Technical Report (TN-29-07): Small-Block vs. Large-Block NAND Flash Devices. Technical Report (TN-29-07): Small-Block vs. Large-Block NAND Flash Devices. http: //www.micron.com/products/nand/technotes.
25. OLTP Trace from UMass Trace Repository. OLTP Trace from UMass Trace Repository. http://traces.cs.umass. edu/index.php/Storage/Storage.
26. Websearch Trace from UMass Trace Repository. Websearch Trace from UMass Trace Repository. http://traces. cs.umass.edu/index.php/Storage/Storage.
27. White Paper: Datacenter SSDs: Solid Footing for Growth. White Paper: Datacenter SSDs: Solid Footing for Growth. http://www.samsung.com/global/ business/semiconductor/products/flash/ FlashApplicationNote.html.
28. J. Zhang, A. Sivasubramaniam, H. Franke, N. Gautam, Y. Zhang, and S. Nagar. Synthesizing Representative I/O Workloads for TPC-H. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), 2004.