Timing analysis for sensor network nodes of the Atmega processor family

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn , Issue , 2005, Pages 405-414

  Mohan, Sibin ^a   Mueller, Frank ^a   Whalley, David ^b   Healy, Christopher ^c  

^a North Carolina State University   (United States)

^b Florida State University   (United States)

^c FURMAN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATMEGA PROCESSOR FAMILY; REAL-TIME SCHEDULABILITY ANALYSIS; SENSOR NETWORK NODES; WCET;

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SIMULATION; CONTROL SYSTEMS; PROGRAM PROCESSORS; SENSORS; TIME AND MOTION STUDY;

EMBEDDED SYSTEMS;

EID: 24944536861     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

1. A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Virtual simple architecture (VISA): Exceeding the complexity limit in safe real-time systems. In International Symposium on Computer Architecture, pages 250-261, June 2003.
2. Atmel. Atmel avr 8-bit rise family. http://www.atmel.com/products/avr/.
3. G. Bernat and A. Burns. An approach to symbolic worst-case execution time analysis. In 25th IFAC Workshop on Real-Time Programming, May 2000.
4. G. Bernat, A. Colin, and S. Petters. WCET analysis of probabilistic hard real-time systems. In IEEE Real-Time Systems Symposium, Dec. 2002.
5. C-Lab. WCET benchmarks. Available from http://www.c-lab.de/home/en/ download.html.
6. R. Chapman, A. Burns, and A. Wellings. Combining static worst-case timing analysis and program proof. Real-Time Systems, 11(2): 145-171, 1996.
7. K. Chen, S. Malik, and D. I. August. Retargetable static timing analysis for embedded software. In Proceedings of the International Symposium on System Synthesis (ISSS), October 2001.
8. J. Engblom. Processor pipelines and static worst-case execution time analysis. Uppsala Dissertations from the Faculty of Science and Technology, 2002.
9. J. Engblom, A. Ermedahl, M. Sjdin, J. Gustafsson, and H. Hansson. Execution-time analysis for embedded real-time systems. In STTT (Software Tools for Technology Transfer) special issue on ASTEC., 2001.
10. D. Estrin, G. Borriello, R. Colwell, J. Fiddler, M. Horowitz, W. Kaiser, N. Leveson, B. Liskov, P. Lucas, D. Maher, P. Mankiewich, R. Taylor, and J. W. (eds.). Embedded, Everywhere, A Research Agenda for Networked Systems of Embedded Computers. Computer Science and Telecommunications Board, National Academies Press, 2001.
11. D. Gay, P. Levis, R. von Behren, M. Welsh, E. Brewer, and D. Culler. The NesC language: A holistic approach to networked embedded systems. In J. J. B. Fenwick and C. Norris, editors, Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI-03), volume 38, 5 of ACM SIGPLAN Notices, pages 1-11, New York, June 9-11 2003. ACM Press.
12. M. Harmon, T. P. Baker, and D. B. Whalley. A retargetable technique for predicting execution time. In IEEE Real-Time Systems Symposium, pages 68-77, Dec. 1992.
13. C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53-70, Jan. 1999.
14. C. A. Healy, M. Sjödin, and D. B. Whalley. Bounding loop iterations for timing analysis. In IEEE Real-Time Embedded Technology and Applications Symposium, pages 12-21, June 1998.
15. C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288-297, Dec. 1995.
16. J. Hill, R. Szewczyk, A. Woo, D. Culler, S. Hollar, and K. Pister. System architecture directions for networked sensors. In Architectural Support for Programming Languages and Operating Systems, pages 93-104, 2000.
17. Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254-263, Dec. 1996.
18. S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, and C. S. Kim. An accurate worst case timing analysis for RISC processors. In IEEE Real-Time Systems Symposium, pages 97-108, Dec. 1994.
19. C. Liu and J. Layland. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. of the Association for Computing Machinery, 20(1):46-61, Jan. 1973.
20. J. Liu. Real-Time Systems. Prentice Hall, 2000.
21. S. Montan and J. Engblom. Validation of a cycle-accurate cpu simulator against real hardware. In ECRTS (Euromicro Conference on Real-Time Systems), 2000.
22. F. Mueller. Timing analysis for instruction caches. Real-Time Systems, 18(2/3):209-239, May 2000.
23. C. Y. Park. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems, 5(1):31-61, Mar. 1993.
24. A. Perrig, R. Szewczyk, V. Wen, D. Culler, and J. D. Tygar. SPINS: Security protocols for sensor networks. In Seventh Annual International Conference on Mobile Computing and Networks (MobiCOM 2001), pages 189-199, 2001.
25. P Puschner and C. Koza. Calculating the maximum execution time of real-time programs. Real-Time Systems, 1(2): 159-176, Sept. 1989.
26. K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. Fast: Frequency-aware static timing analysis. In IEEE Real-Time Systems Symposium, pages 40-51, Dec. 2003.
27. S. Thesing, J. Souyris, R. Heckmann, F. R. andM. Langenbach, R. Wilhelm, and C. Ferdinand. An Abstract Interpretation-Based Timing Validation of Hard Real-Time Avionics. In Proceedings of the International Performance and Dependability Symposium (IPDS), June 2003.
28. E. Vivancos, C. Healy, F. Mueller, and D. Whalley. Parametric timing analysis. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Embedded Systems, volume 36 of ACM SIGPLAN Notices, pages 88-93, Aug. 2001.
29. D. L. Weaver and T. Germond. The SPARC Architecture Manual - Version 9. Prentice Hall, 1994.
30. J. Wegener and F. Mueller. A comparison of static analysis and evolutionary testing for the verifi cation of timing constraints. Real-Time Systems, 21(3):241-268, Nov. 2001.
31. R. White, F. Mueller, C. Healy, D. Whalley, and M. Harmon. Timing analysis for data caches and set-associative caches. In IEEE Real-Time Embedded Technology and Applications Symposium, pages 192-202, June 1997.
32. R. T. White, F. Mueller, C. Healy, D. Whalley, and M. G. Harmon. Timing analysis for data and wrap-around fill caches. Real-Time Systems, 17(2/3):209-233, Nov. 1999.