Coordinating prefetching and STT-RAM based last-level cache management for multicore systems

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2013, Pages 55-60

  Mao, Mengjie ^a   Li, Hai ^a   Jones, Alex K ^a   Chen, Yiran ^a  

^a University of Pittsburgh   (United States)

Author keywords

cache management; prefetching; stt ram

Indexed keywords

CACHE MANAGEMENT; LOW-POWER CONSUMPTION; OFF-CHIP COMMUNICATION; PERFORMANCE DEGRADATION; PRE-FETCHING SCHEME; PREFETCHING; SPIN-TRANSFER TORQUE RANDOM ACCESS MEMORY (STT-RAM); STT RAMS;

STATIC RANDOM ACCESS STORAGE;

EID: 84878168739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2483028.2483060     Document Type: Conference Paper

References (18)

1. J. Doweck. Inside intel core microarchitecture and smart memory access. Intel White Paper, 2006.
2. C.-K. Luk et al. Pin: Building customized program analysis tools with dynamic instrumentation. In PLDI, pages 190-200, June 2005.
3. E. Ebrahimi et al. Coordinated control of multiple prefetchers in multi-core systems. In MICRO, pages 316-326, 2009.
4. E. Ebrahimi et al. Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. In HPCA, pages 7-17, 2009.
5. E. Ebrahimi et al. Prefetch-aware shared resource management for multi-core systems. In ISCA, pages 141-152, 2011.
6. G. Sun et al. A novel architecture of the 3d stacked mram l2 cache for cmps. In HPCA, pages 239-249, 2009.
7. J. Tendler et al. Power4 system microarchitecture. IBM Technical White Paper, Oct. 2001.
8. M. Hosomi et al. A novel non-volatile memory with spin torque transfer magnetization switching: Spin-ram. In IEDM, pages 459-462, 2005.
9. O. Mutlu et al. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO, pages 146-160, 2007.
10. S. Eyerman et al. System-level performance metrics for multiprogram workloads. IEEE Micro, 28(3):42-53, 2008.
11. S. Srinath et al. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In HPCA, pages 63-74, 2007.
12. T. Sherwood et al. Basic block distribution analysis to find periodic behavior and simulation points in applications. In PACT, pages 3-14, 2001.
13. W.-F. Lin et al. Filtering superfluous prefetches using density vectors. In ICCD, 2001.
14. W. Zhao et al. Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-cmos design. In IBMSW, pages 40-43, 2006.
15. X. Dong et al. Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE TCAD of ICS, 31(7):994-1007, 2012.
16. X. Wu et al. Hybrid cache architecture with disparate memory technologies. In ISCA, pages 34-45, 2009.
17. X. Zhuang et al. A hardware-based cache pollution filtering mechanism for aggressive prefetchers. In ICPP, 2003.
18. MacSim. http://code.google.com/p/macsim/.