A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch

Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012

Volumn , Issue , 2012, Pages 247-257

  Sim, Jaewoong ^a   Loh, Gabriel H ^c   Kim, Hyesoon ^b   Oconnor, Mike ^c   Thottethodi, Mithuna ^d  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE COST; HARDWARE OVERHEADS; IMPROVE PERFORMANCE; OFF-CHIP MEMORY; PERFORMANCE BENEFITS; SELF-BALANCING; VERIFICATION PROCESS; WRITE POLICIES;

COMPUTER ARCHITECTURE; HARDWARE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84876515756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2012.31     Document Type: Conference Paper

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