Dimensional optimization of nanowire - Complementary metal oxide-semiconductor inverter

Journal of Nanoscience and Nanotechnology

Volumn 13, Issue 1, 2013, Pages 242-249

  Hashim, Yasir ^a   Sidek, Othman ^a  

^a SCHOOL OF CHEMICAL ENGINEERING   (Malaysia)

Author keywords

CMOS; Inverter; Nanowire; Transistor

Indexed keywords

CHANNEL LENGTH; DIGITAL VOLTAGE; INVERTER; METAL OXIDE SEMICONDUCTOR; NOISE MARGINS; OXIDE SEMICONDUCTOR; SILICON NANOWIRE TRANSISTORS; TRANSFER CHARACTERISTICS;

CMOS INTEGRATED CIRCUITS; NANOWIRES; TRANSISTORS;

OPTIMIZATION;

METAL; NANOMATERIAL; OXIDE;

ARTICLE; CHEMISTRY; COMPUTER AIDED DESIGN; ELECTRIC CONDUCTIVITY; EQUIPMENT; EQUIPMENT DESIGN; EQUIPMENT FAILURE; SEMICONDUCTOR; SIGNAL PROCESSING; ULTRASTRUCTURE;

COMPUTER-AIDED DESIGN; ELECTRIC CONDUCTIVITY; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; METALS; NANOSTRUCTURES; OXIDES; SEMICONDUCTORS; SIGNAL PROCESSING, COMPUTER-ASSISTED; TRANSISTORS, ELECTRONIC;

MLCS; MLOWN;

EID: 84876256845     PISSN: 15334880     EISSN: 15334899     Source Type: Journal    
DOI: 10.1166/jnn.2013.6796     Document Type: Article

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