Study and simulation of static characteristics of nanowire inverter with different circuit configurations

International Review on Modelling and Simulations

Volumn 5, Issue 1, 2012, Pages 93-98

  Hashim, Yasir ^a   Sidek, Othman ^b  

^a SCHOOL OF PHYSICS   (Malaysia)

^b Universiti Sains Malaysia Engineering Campus   (Malaysia)

Author keywords

CMOS; Inverter; Nanowire; NMOS; Transistor

Indexed keywords

EID: 84865583559     PISSN: 19749821     EISSN: 25331701     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

1. M. Bescond, K. Nehari, J.L. Autran, N. Cavassilas, D. Munteanu, M. Lannoo, 3D quantum modeling and simulation of multiplegate nanowire MOSFET, IEDM Tech. Dig., p. 617, 2004.
2. Ramses V Martínez, Javier Martínez, Ricardo Garcia, Silicon nanowire circuits fabricated by AFM oxidation nanolithography, Nanotechnolog Vol. 21, No. 24, 2009.
3. K. Nehari, N. Cavassilas, J. L. Autran, M. Bescond, D. Munteanu, M. Lannoo, Influence of band-structure on electron ballistic transport in Silicon nanowire MOSFET's: an atomistic study, Proc. ESSDERC 2005, p. 229, 2005.
4. J. Wang, E. Polizzi, M. S. Lundstrom, A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation, J. Appl. Phys., vol. 96, p. 2192, 2004.
5. S. C. Rustagi, N. Singh, W. W. Fang, K. D. Buddharaju, S. R. Omampuliyur, S. H. G. Teo, C. H. Tung, G. Q. Lo, N. Balasubramanian, D. L. Kwong, CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach, IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 11, pp 1021-1024 November 2007.
6. E. Gnani et al., Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs, ESSDERC Proceeding, 2006, pp. 371-374.
7. N. Balasubramanian et al., Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach, ECS Transactions, 13 (1), PP 201-211 (2008).
8. https://nanohub.org/resources/NANOFINFET
9. P. Lloyd et al., Technology CAD at AT&T, Microelectronics Journal, 26(1995), 79-97.
10. Ebrahimi, et al., A 1.2V High Band-Width Analog Multiplier in 0.18μm CMOS Technology, International Review of Electrical Engineering (IREE), Vol. 5 No. 2 Part B, PP 803-811, (2010).
11. S. Reza. Talebiyan, Saied. Hosseini-Khayat, A Low Leakage Power Adder Structure for Nano-Scale CMOS, International Review on Modelling and Simulations (IREMOS), Vol. 1 No. 2, PP 281-284, (2008).
12. S. Reza Talebiyan, Saied Hosseini-Khayat, Fast Low Power Adder Design for Deep Submicron CMOS, International Review on Modelling and Simulations (IREMOS), Vol. 2 No. 1, PP 8-11, (2009).
13. M. Lee, Y. Jeon, T. Moon, and S. Kim, Top-Down Fabrication of Fully CMOS-Compatible Silicon Nanowire Arrays and Their Integration into CMOS Inverters on Plastic, ACS-NANO, VOL. 5 NO. 4, PP 2629-2636, 2011.