Reconciling performance and programmability in networking systems

Computer Communication Review

Volumn 37, Issue 4, 2007, Pages 73-84

  Mudigonda, Jayaram ^a,b   Vin, Harrick M ^a   Keckler, Stephen W ^a  

^a University of Texas at Austin   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Data cache; Memory bottleneck; Multithreading; Packet processing; Processor architectures; Reconfigurable architectures; Routers

Indexed keywords

DATA CACHES; MEMORY BOTTLENECK; MULTI-THREADING; PACKET PROCESSING; PROCESSOR ARCHITECTURES;

DYNAMIC MODELS; NETWORK ARCHITECTURE; PACKET NETWORKS; RECONFIGURABLE ARCHITECTURES; ROUTERS;

MULTITASKING;

EID: 84876220724     PISSN: 01464833     EISSN: 19435819     Source Type: Conference Proceeding    
DOI: 10.1145/1282427.1282390     Document Type: Article

References (38)

1. CACTI3.2 http://tinyurl.com/yqu8a5.
2. Global Environment for Network Innovations. http://www.geni.net.
3. Intel IXA SDK 3.0. http://tinyurl.com/2ltuwu.
4. Internet RFC Archive. http://www.faqs.org/rfcs/.
5. NPF Benchmarks; http://tinyurl.com/2rbz6g.
6. Simplescalar 3.0. http://www.simplescalar.com/.
7. Snort IDS; http://www.snort.org.
8. University of Oregon Route Views Project. http://www.routeviews.org/.
9. J.-L. Baer, D. Low, P. Crowley, and N. Sidhwaney. Memory hierarchy design for a multiprocessor look-up engine. In Proc. of the IEEE Conf. on Parallel Architectures and Compilation Techniques, pages 206-216, 2003.
10. M. Bjorkman and P. Gunningberg. Locking Effects in Multiprocessor Implementations of Protocols. In Proc. of the ACM SIGCOMM Conf. on Communications, pages 74-83, 1993.
11. J. A. Butts and G. S. Sohi. Use-based register caching with decoupled indexing. In Proc. of the ACM Intl. Symp. on Computer Architecture, pages 302-313, 2004.
12. T.-C. Chiueh and P. Pradhan. Cache Memory Design for Network Processors. In Proc. of the Intl. Symp. on High-Performance Computer Architecture, pages 409-418, 2000.
13. P. Crowley, M. E. Fiuczynski, and J.-L. Baer. Characterizing Processor Architectures for Programmable Network Interfaces. In Proc. of the Intl. Conf. on Super Computing, pages 54-65, 2000.
14. P. Crowley, M. E. Fiuczynski, and J.-L. Baer. On the Performance of Multithreaded Architectures for Network Processors. Technical Report TR2000-10-01, University of Washington, 2000.
15. W. Eatherton. "The Push of the Network Processing to the Top of the Pyramid", Keynote at the Symp. on Architectures for Networking and Communications Systems, 2005.
16. W. Eatherton, G. Varghese, and Z. Dittia. Tree bitmap: hardware/software IP lookups with incremental updates. ACM SIGCOMM Computer Communication Review, 34(2):97-122, 2004.
17. C. Estan and G. Varghese. New directions in traffic measurement and accounting. In Proc. of the Internet Measurement Workshop, pages 75-80, 2001.
18. P. Gupta and N. McKeown. Algorithms for Packet Classification. In IEEE Network - The Magazine of Global Internetworking, pages 24-32, March 2001.
19. J. Hasan, S. Chandra, and T. N. Vijaykumar. Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. In Proc. of the ACM Intl. Symp. on Computer Architecture, pages 300-313, 2003.
20. S. Iyer, R. R. Kompella, and N. McKeown. Analysis of Memory Architecture for Fast Packet Buffers. In Proc. of the IEEE Workshop on High Performance Switching and Routing, pages 368-373, 2001.
21. E. J. Johnson and A. Kunze. IXP 2800 Programming. Intel Press, 2003.
22. S. Kumar and P. Crowley. Segmented hash: an efficient hash table implementation for high performance networking subsys. In Proc. of the Symp. on Architectures for Networking and Communications Systems, pages 91-103, 2005.
23. G. Memik, W. H. Mangione-Smith, and W. Hu. NetBench: A Benchmarking Suite for Network Processors. In Proc. of the IEEE/ACM Conf. on Computer-Aided Design, pages 39-42, 2001.
24. J. Mudigonda. Addressing the Memory Bottleneck in Packet Processing Systems. PhD thesis, Universtity of Texas at Austin, 2005.
25. J. Mudigonda, H. M. Vin, and R. Yavatkar. Managing Memory Access Latency in Packet Processing. In Proc. of the ACM Conf. on Measurement and Modeling of Computer Systems, pages 396-397, 2005.
26. NLANR Network Traffic Packet Header Traces. http://pma.nlanr.net/Traces/.
27. C. Partridge et al. A 50-Gb/s IP router. IEEE/ACM Transactions on Networking, 6(3):237-248, 1998.
28. M. Postiff, D. Greene, S. Raasch, and T. Mudge. Integrating superscalar processor components to implement register caching. In Proc. of the Intl. Conf. on Super Computing, pages 348-357, 2001.
29. K. Sankaralingam et al. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. In Proc. of the ACM Intl. Symp. on Computer Architecture, pages 422-433, 2003.
30. T. Sherwood, G. Varghese, and B. Calder. A Pipelined Memory Architecture for High Throughput Network Processors. In Proc. of the ACM Intl. Symp. on Computer Architecture, pages 288-299, 2003.
31. K. Sklower. A Tree-Based Packet Routing Table for Berkeley Unix. In Proc. of the Winter USENIX Conference, pages 93-103, 1991.
32. J. Smith, E. Cooper, B. Davie, I. Leslie, Y. Ofek, and R. Watson, editors. IEEE Journal on Selected Areas in Communications (JSAC). IEEE, Feb 1993.
33. H. Song, S. Dharmapurikar, J. Turner, and J. Lockwood. Fast hash table lookup using extended bloom filter: an aid to network processing. In Proc. of the ACM SIGCOMM Conf. on Communications, pages 181-192, 2005.
34. V. Soundararajan. Dribble-back registers: A technique for latency tolerance in multiprocessors. Technical Report Technical Memo-474, LCS, MIT, 1992.
35. G. Varghese. Network Algorithmics: An Interdisciplinary Approach to Designing Fast Networked Devices. M. Kaufmann, 2004.
36. T. Wolf and M. Franklin. CommBench-A Telecommunications Benchmark for Network Processors. In Proc. of the Intl. Symp. on Performance Analysis of Systems and Software, pages 154-162, 2000.
37. S. Wu and U. Manber. A Fast Algorithm for Multi-pattern Searching. Technical Report TR-94-17, University of Arizona, 1994.
38. J. Xu, M. Singhal, and J. Degroat. A Novel Cache Architecture to Support Layer-Four Packet Classification at Memory Access Speeds. In Proc. of the IEEE Conf. on Computer Communications, pages 1445-1454, 2000.