Managing memory access latency in packet processing

Performance Evaluation Review

Volumn 33, Issue 1, 2005, Pages 396-397

  Mudigonda, Jayaram ^a   Vin, Harrick M ^a   Yavatkar, Raj ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Data caches; Multithreading; Network processors

Indexed keywords

BANDWIDTH; BUFFER STORAGE; COMPUTER SYSTEMS PROGRAMMING; DATA ACQUISITION; DATA STORAGE EQUIPMENT;

DATA-CACHES; DATA-CACHING; MULTITHREADING; NETWORK PROCESSORS;

PACKET NETWORKS;

EID: 33244477678     PISSN: 01635999     EISSN: 01635999     Source Type: Conference Proceeding    
DOI: 10.1145/1071690.1064272     Document Type: Conference Paper

References (3)

1. D. Comer. Network Systems Design Using Network Processors. Prentice Hall, ISBN 0-13-141792-4, 2003.
2. P. C. Lekkas. Network Processors: Architectures, Protocols and Platforms. McGraw-Hill Profesional, 1 edition, July 2003.
3. J. Mudigonda, H. M. Vin, and R. Yavatkar. Managing Memory Access Latency in Packet Processing Systems. Technical Report TR-05-11, University of Texas at Austin, 2005.