Cache memory design for network processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 409-418

  Chiueh, Tzi Cker ^a   Pradhan, Prashant ^a  

^a Stony Brook University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER SIMULATION; INTERNET; PACKET NETWORKS; ROUTERS; TELECOMMUNICATION TRAFFIC;

INTERNET TRAFFIC; NETWORK PROCESSORS; TEMPORAL LOCALITY;

MULTIPROCESSING SYSTEMS;

EID: 0034581191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. Design and implementation of a qos capable switch-router
2. Effect of caching on routing-table lookup in multimedia environments
3. High performance ip routing table lookup using cpu caching
4. Gigapower protocol processor
5. Routing on longest matching prefixes
6. An assessment of state and lookup overhead in routers
7. Improving gateway performance with a routing-table cache
8. Characteristics of destination address locality in computer networks: A comparison of caching schemes
9. Longest match engine
10. The integrated network services switch: A new architecture for emerging applications
11. 20 mpps network processor with wire-speed layer 3 processing for building switches and routers
12. Streamprocessor 2400 backbone switch router
13. Locality and route caches
14. A fifty gigabit per second ip router
15. Operating systems support for programmable cluster-based internet routers
16. The world of terabit switch/router technology
17. Next generation internet router
18. High-speed routing table search algorithms
19. The ip9000 gigabit router architecture
20. Internet performance management and analysis (ipma) project
21. Scalable high speed ip routing lookups
22. Small forwarding tables for fast routing lookups