Memory hierarchy design for a multiprocessor look-up engine

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2003-January, Issue , 2003, Pages 206-216

  Baer, J L ^a   Low, D ^a   Crowley, P ^a   Sidhwaney, N ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT DESIGN; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS;

BRANCHING FACTORS; MAIN PARAMETERS; MEMORY ACCESS; MEMORY CAPACITY; MEMORY HIERARCHY; OFF-CHIP MEMORY; ON-CHIP CACHE; ROUTING TABLE;

CACHE MEMORY;

EID: 84968830512     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1238016     Document Type: Conference Paper

References (16)

1. T. Chiueh and P. Pradhan. High-performance IP routing table lookup using CPU caching. In Proc. IEEE Infocom, pages 1421-1428, 1999.
2. T. Chiueh and P. Pradhan. Cache memory design for network processors. In Proc. 6th Int. Symp. on High-Performance Computer Architecture, pages 409-418, 2000.
3. P. Crowley, M. Fiuczynski, J.-L. Baer, and B. Bershad. Characterizing processor architectures for programmable network interfaces. In Proc. Int. Conf. on Supercomputing, pages 54-65, 2000.
4. D.Shah and P.Gupta. Fast updating algoritms for TCAMs. IEEE Micro, 21(1), Jan. 2001.
5. The role of network processors in next generation networks. http://developer.intel.com/design/network/papers/279048.htm, 2001.
6. D. Knuth. The Art of Computer Programming. Vol 3, Searching and Sorting. Addison-Wesley, Reading, Ma, 1973.
7. J. Marshall. Cisco systems - Toaster 2. In P.Crowley et al., editor, Network Processor Design, pages 235-248. Morgan-Kaufmann, 2003.
8. IPMA reports. http://www.merit.edu/ipma/reports, 2002.
9. G. Narlikar and F. Zane. Performance modeling for fast IP lookups. In Proc. of ACM SIGMETRICS, 2001.
10. S. Nilsson and G. Karlson. IP-address lookup using LC-Tries. IEEE Journal on Selected Areas in Communications, 17(6):1083-1092, June 1999.
11. M. O'Connor and C. Gomez. The iFlow address processor. IEEE Micro, 21(2):16-23, Mar. 2001.
12. L. Peterson and B. Davie. Computer Networks: A systems approach - 2nd Ed. Morgan Kaufman, San Francisco, Ca, 2000.
13. T. Sherwood, G. Varghese, and B. Calder. Suporting network algorithms with a pipelined architecture. In Proc. of ISCA 2003, 2003.
14. S.Keshav and R. Sharma. Issues and trends in router design. IEEE Communications magazine, pages 144-151, May 1998.
15. V. Srinivasan and G. Varghese. Fast address lookups using controlled prefix expansion. ACM TOCS, 17(1):1-40, Feb. 1999.
16. M. Waldvogel, G. Varghese, J. Turner, and B. Plattner. Scalable high-speed prefix matching. ACM TOCS, 19(4):440-482, Nov. 2001.