FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 60, Issue 1, 2013, Pages 36-40

  Wang, Yi ^a   Ha, Yajun ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Advanced encryption standard (AES); differential power analysis (DPA); field programmable gate array (FPGA); masking; storage area network (SAN)

Indexed keywords

COMPUTER NETWORKS; DATA PRIVACY; ENGINES; INVERSE PROBLEMS; ITERATIVE METHODS; LOGIC GATES; MAPPING; RANDOM ACCESS STORAGE; RISK ASSESSMENT; SIDE CHANNEL ATTACK; SPEECH INTELLIGIBILITY;

ADVANCED ENCRYPTION STANDARD; AREA OPTIMIZATION; DIFFERENTIAL POWER ANALYSIS; DIFFERENTIAL POWER ANALYSIS ATTACK; HARDWARE RESOURCES; HIGH THROUGHPUT; STATE OF THE ART; STORAGE AREA NETWORKS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84874945297     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2234891     Document Type: Article

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