53 Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45 nm high-performance microprocessors

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 4, 2011, Pages 767-776

  Mathew, Sanu K ^a   Sheikh, Farhana ^a   Kounavis, Michael ^a   Gueron, Shay ^b,c   Agarwal, Amit ^a   Hsu, Steven K ^a   Kaul, Himanshu ^a   Anders, Mark A ^a   Krishnamurthy, Ram K ^a  

^a INTEL CORPORATION   (United States)

^b INTEL CORPORATION   (Israel)

^c UNIVERSITY OF HAIFA   (Israel)

Author keywords

Advanced encryption standard; AES; content protection; cryptography hardware accelerator; encryption; native Galois field inversion; security co processor; special purpose hardware accelerator

Indexed keywords

ADVANCED ENCRYPTION STANDARD; AES; CONTENT PROTECTION; ENCRYPTION; NATIVE GALOIS-FIELD INVERSION; SECURITY CO-PROCESSOR; SPECIAL-PURPOSE HARDWARE ACCELERATOR;

ACCELERATION; COMPUTER HARDWARE; ENERGY EFFICIENCY; HARDWARE; MICROPROCESSOR CHIPS; RECONFIGURABLE HARDWARE; VLSI CIRCUITS;

CRYPTOGRAPHY;

EID: 79953209640     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2108131     Document Type: Article

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